Patrick Georgi submitted this change.
soc/amd/picasso: Put transfer buffer into common ld file
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.
BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
M src/soc/amd/picasso/memlayout_psp_verstage.ld
A src/soc/amd/picasso/memlayout_transfer_buffer.inc
M src/soc/amd/picasso/memlayout_x86.ld
3 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld
index 4ad88b1..e7a6c84 100644
--- a/src/soc/amd/picasso/memlayout_psp_verstage.ld
+++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld
@@ -51,16 +51,7 @@
ALIGN_COUNTER(64)
_everstage = .;
- ALIGN_COUNTER(64)
- _transfer_buffer = .;
- REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4)
- ALIGN_COUNTER(64)
- REGION(vboot2_work, ., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, 64)
- ALIGN_COUNTER(64)
- PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
- TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
- FMAP_CACHE(., FMAP_SIZE)
- _etransfer_buffer = .;
+ #include "memlayout_transfer_buffer.inc"
PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE );
diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/picasso/memlayout_transfer_buffer.inc
new file mode 100644
index 0000000..a88e81a
--- /dev/null
+++ b/src/soc/amd/picasso/memlayout_transfer_buffer.inc
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if CONFIG(VBOOT)
+ ALIGN_COUNTER(64)
+ _transfer_buffer = .;
+ REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4)
+
+ ALIGN_COUNTER(64)
+ VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
+#endif
+
+ ALIGN_COUNTER(64)
+ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+ TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
+ FMAP_CACHE(., FMAP_SIZE)
+
+#if CONFIG(VBOOT)
+ _etransfer_buffer = .;
+#endif
diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld
index 00cdde6..eeb6dda 100644
--- a/src/soc/amd/picasso/memlayout_x86.ld
+++ b/src/soc/amd/picasso/memlayout_x86.ld
@@ -75,16 +75,11 @@
#if CONFIG(VBOOT)
PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
- _transfer_buffer = .;
- REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4)
- VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
#endif
- PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
- TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
- FMAP_CACHE(., FMAP_SIZE)
+#include "memlayout_transfer_buffer.inc"
+
#if CONFIG(VBOOT)
- _etransfer_buffer = .;
PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
#endif
_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
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