Tim Wawrzynczak submitted this change.
mb/google/volteer/var/voxel: Add Raydium touchscreen support
Update gpio GPP_E7 and enable the Raydium TS support
BUG=b:157402209,b:162632701,b:162636271
BRANCH=master
TEST= 1. emerge-volteer coreboot chromeos-bootimage
2. boot up on voxel DUT and make sure the raydium TS can work.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
---
M src/mainboard/google/volteer/variants/voxel/gpio.c
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c
index a460fff..b65e813 100644
--- a/src/mainboard/google/volteer/variants/voxel/gpio.c
+++ b/src/mainboard/google/volteer/variants/voxel/gpio.c
@@ -117,7 +117,7 @@
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
PAD_CFG_GPO(GPP_E3, 1, DEEP),
/* E7 : CPU_GP1 ==> USI_INT */
- PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
/* E8 : SPI1_CS1# ==> SLP_S0IX */
PAD_CFG_GPO(GPP_E8, 0, DEEP),
/* E10 : SPI1_CS# ==> NC(TP94508) */
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 2219de0..43296d5 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -63,6 +63,20 @@
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
+ chip drivers/i2c/generic
+ register "hid" = ""RAYD0001""
+ register "desc" = ""Raydium Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+ register "reset_delay_ms" = "1"
+ register "reset_off_delay_ms" = "2"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+ register "enable_delay_ms" = "10"
+ register "enable_off_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 39 on end
+ end
end # I2C1 0xA0E9
device pci 15.2 on
chip drivers/i2c/sx9310
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