Edward O'Callaghan has uploaded this change for review.
mainboard/google: Shim out Puff board
TODO: devicetree.
Workout a way to fold this back into Hatch.
Change-Id: Icc8b13471e6e0b8cf540c35c712089c3205a3497
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
---
A src/mainboard/google/puff/Kconfig
A src/mainboard/google/puff/Kconfig.name
A src/mainboard/google/puff/Makefile.inc
A src/mainboard/google/puff/acpi_tables.c
A src/mainboard/google/puff/board_info.txt
A src/mainboard/google/puff/bootblock.c
A src/mainboard/google/puff/chromeos-16MiB.fmd
A src/mainboard/google/puff/chromeos.c
A src/mainboard/google/puff/chromeos.fmd
A src/mainboard/google/puff/dsdt.asl
A src/mainboard/google/puff/ec.c
A src/mainboard/google/puff/mainboard.asl
A src/mainboard/google/puff/mainboard.c
A src/mainboard/google/puff/ramstage.c
A src/mainboard/google/puff/romstage.c
A src/mainboard/google/puff/smihandler.c
A src/mainboard/google/puff/variants/baseboard/Makefile.inc
A src/mainboard/google/puff/variants/baseboard/devicetree.cb
A src/mainboard/google/puff/variants/baseboard/gpio.c
A src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl
A src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
A src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/puff/variants/baseboard/memory.c
A src/mainboard/google/puff/variants/puff/Makefile.inc
A src/mainboard/google/puff/variants/puff/gpio.c
A src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl
A src/mainboard/google/puff/variants/puff/include/variant/ec.h
A src/mainboard/google/puff/variants/puff/include/variant/gpio.h
A src/mainboard/google/puff/variants/puff/overridetree.cb
30 files changed, 2,186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36065/1
diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig
new file mode 100644
index 0000000..0c49d6a
--- /dev/null
+++ b/src/mainboard/google/puff/Kconfig
@@ -0,0 +1,109 @@
+
+config BOARD_GOOGLE_BASEBOARD_PUFF
+ def_bool n
+ select DRIVERS_GENERIC_GPIO_KEYS
+ select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_DA7219
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_I2C_SX9310
+ select DRIVERS_SPI_ACPI
+ select DRIVERS_USB_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_BOARDID
+ select EC_GOOGLE_CHROMEEC_ESPI
+ select GOOGLE_SMBIOS_MAINBOARD_VERSION
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_SPI_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
+ select SOC_INTEL_COMETLAKE
+ select SYSTEM_TYPE_LAPTOP
+
+if BOARD_GOOGLE_BASEBOARD_PUFF
+
+config CHROMEOS
+ bool
+ default y
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+config CHROMEOS_WIFI_SAR
+ bool "Enable SAR options for Chrome OS build"
+ depends on CHROMEOS
+ select DSAR_ENABLE
+ select GEO_SAR_ENABLE
+ select SAR_ENABLE
+ select USE_SAR
+ select WIFI_SAR_CBFS
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
+config UART_FOR_CONSOLE
+ default 0
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768
+
+config MAINBOARD_DIR
+ string
+ default "google/puff"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Puff"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Puff" if BOARD_GOOGLE_PUFF
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config MAX_CPUS
+ int
+ default 8
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 53 # GPE0_DW1_21 (GPP_C21)
+
+config VARIANT_DIR
+ string
+ default "puff" if BOARD_GOOGLE_PUFF
+
+config VBOOT
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_BASEBOARD_PUFF
diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name
new file mode 100644
index 0000000..61c4e0f
--- /dev/null
+++ b/src/mainboard/google/puff/Kconfig.name
@@ -0,0 +1,6 @@
+comment "Puff"
+
+config BOARD_GOOGLE_PUFF
+ bool "-> Puff"
+ select BOARD_GOOGLE_BASEBOARD_PUFF
+ select BOARD_ROMSIZE_KB_32768
diff --git a/src/mainboard/google/puff/Makefile.inc b/src/mainboard/google/puff/Makefile.inc
new file mode 100644
index 0000000..adab446
--- /dev/null
+++ b/src/mainboard/google/puff/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-y += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/puff/acpi_tables.c b/src/mainboard/google/puff/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/google/puff/acpi_tables.c
diff --git a/src/mainboard/google/puff/board_info.txt b/src/mainboard/google/puff/board_info.txt
new file mode 100644
index 0000000..1168548
--- /dev/null
+++ b/src/mainboard/google/puff/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Puff
+Category: desktop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/puff/bootblock.c b/src/mainboard/google/puff/bootblock.c
new file mode 100644
index 0000000..15dfe93
--- /dev/null
+++ b/src/mainboard/google/puff/bootblock.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+
+static void early_config_gpio(void)
+{
+ const struct pad_config *variant_early_table;
+ size_t variant_gpios;
+
+ variant_early_table = variant_early_gpio_table(&variant_gpios);
+ gpio_configure_pads(variant_early_table, variant_gpios);
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
diff --git a/src/mainboard/google/puff/chromeos-16MiB.fmd b/src/mainboard/google/puff/chromeos-16MiB.fmd
new file mode 100644
index 0000000..eb92bb0
--- /dev/null
+++ b/src/mainboard/google/puff/chromeos-16MiB.fmd
@@ -0,0 +1,43 @@
+FLASH@0xff000000 0x1000000 {
+ SI_ALL@0x0 0x400000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x3ff000
+ }
+ SI_BIOS@0x400000 0xc00000 {
+ RW_SECTION_A@0x0 0x368000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x357fc0
+ RW_FWID_A@0x367fc0 0x40
+ }
+ RW_SECTION_B@0x368000 0x368000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x357fc0
+ RW_FWID_B@0x367fc0 0x40
+ }
+ RW_MISC@0x6D0000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x20000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ }
+ RW_ELOG(PRESERVE)@0x20000 0x4000
+ RW_SHARED@0x24000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x28000 0x2000
+ RW_NVRAM(PRESERVE)@0x2a000 0x6000
+ }
+ # RW_LEGACY needs to be minimum of 1MB
+ RW_LEGACY(CBFS)@0x700000 0x100000
+ WP_RO@0x800000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x3fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x30c000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/puff/chromeos.c b/src/mainboard/google/puff/chromeos.c
new file mode 100644
index 0000000..4119670
--- /dev/null
+++ b/src/mainboard/google/puff/chromeos.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
+}
diff --git a/src/mainboard/google/puff/chromeos.fmd b/src/mainboard/google/puff/chromeos.fmd
new file mode 100644
index 0000000..45dbc81
--- /dev/null
+++ b/src/mainboard/google/puff/chromeos.fmd
@@ -0,0 +1,47 @@
+FLASH@0xfe000000 0x2000000 {
+ SI_ALL@0x0 0x400000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x3ff000
+ }
+ SI_BIOS@0x400000 0x1c00000 {
+ # Place RW_LEGACY at the start of BIOS region such that the rest
+ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB
+ # SPI flash only the top 16MiB actually gets memory mapped.
+ RW_LEGACY(CBFS)@0x0 0x1000000
+ RW_SECTION_A@0x1000000 0x3e0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x3cffc0
+ RW_FWID_A@0x3dffc0 0x40
+ }
+ RW_SECTION_B@0x13e0000 0x3e0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x3cffc0
+ RW_FWID_B@0x3dffc0 0x40
+ }
+ RW_MISC@0x17c0000 0x40000 {
+ UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x20000
+ }
+ RW_ELOG(PRESERVE)@0x30000 0x4000
+ RW_SHARED@0x34000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x38000 0x2000
+ RW_NVRAM(PRESERVE)@0x3a000 0x6000
+ }
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO@0x1800000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x3fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x30c000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/puff/dsdt.asl b/src/mainboard/google/puff/dsdt.asl
new file mode 100644
index 0000000..e2959a7
--- /dev/null
+++ b/src/mainboard/google/puff/dsdt.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ /* Some generic macros */
+ #include <soc/intel/cannonlake/acpi/platform.asl>
+
+ /* global NVS and variables */
+ #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/cannonlake/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ /* Mainboard hooks */
+ #include "mainboard.asl"
+ }
+
+#if CONFIG(CHROMEOS)
+ /* Chrome OS specific */
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+ /* Low power idle table */
+ #include <soc/intel/cannonlake/acpi/lpit.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include <variant/acpi/dptf.asl>
+ /* Include soc specific DPTF changes */
+ #include <soc/intel/cannonlake/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <soc/intel/common/acpi/dptf/dptf.asl>
+ }
+}
diff --git a/src/mainboard/google/puff/ec.c b/src/mainboard/google/puff/ec.c
new file mode 100644
index 0000000..9fb3d80
--- /dev/null
+++ b/src/mainboard/google/puff/ec.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+ const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/puff/mainboard.asl b/src/mainboard/google/puff/mainboard.asl
new file mode 100644
index 0000000..dff1a75
--- /dev/null
+++ b/src/mainboard/google/puff/mainboard.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+ For (Local0 = 0, Local0 < 5, Local0++)
+ {
+ \_SB.PCI0.CGPM (Local0, Arg0)
+ }
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+ LOCL (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+ If (Arg0 == 1) {
+ /* S0ix Entry */
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ } Else {
+ /* S0ix Exit */
+ LOCL (0)
+ }
+}
diff --git a/src/mainboard/google/puff/mainboard.c b/src/mainboard/google/puff/mainboard.c
new file mode 100644
index 0000000..5761b08
--- /dev/null
+++ b/src/mainboard/google/puff/mainboard.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <smbios.h>
+#include <string.h>
+#include <stdint.h>
+
+#define SKU_UNKNOWN 0xFFFFFFFF
+#define SKU_MAX 255
+
+uint32_t get_board_sku(void)
+{
+ static uint32_t sku_id = SKU_UNKNOWN;
+
+ if (sku_id != SKU_UNKNOWN)
+ return sku_id;
+
+ if (google_chromeec_cbi_get_sku_id(&sku_id))
+ sku_id = SKU_UNKNOWN;
+
+ return sku_id;
+}
+
+const char *smbios_system_sku(void)
+{
+ static char sku_str[7]; /* sku{0..255} */
+ uint32_t sku_id = get_board_sku();
+
+ if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) {
+ printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n",
+ __func__, sku_id);
+ return "";
+ }
+
+ snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
+
+ return sku_str;
+}
+
+const char *smbios_mainboard_manufacturer(void)
+{
+ static char oem_name[32];
+ static const char *manuf;
+
+ if (manuf)
+ return manuf;
+
+ if (google_chromeec_cbi_get_oem_name(&oem_name[0],
+ ARRAY_SIZE(oem_name)) < 0) {
+ printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n");
+ manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
+ } else {
+ manuf = &oem_name[0];
+ }
+
+ return manuf;
+}
diff --git a/src/mainboard/google/puff/ramstage.c b/src/mainboard/google/puff/ramstage.c
new file mode 100644
index 0000000..04e1bc1
--- /dev/null
+++ b/src/mainboard/google/puff/ramstage.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <ec/ec.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ const struct pad_config *base_table;
+ const struct pad_config *override_table;
+ size_t base_gpios;
+ size_t override_gpios;
+
+ variant_devtree_update();
+ base_table = base_gpio_table(&base_gpios);
+ override_table = override_gpio_table(&override_gpios);
+
+ gpio_configure_pads_with_override(base_table,
+ base_gpios,
+ override_table,
+ override_gpios);
+}
+
+void __weak variant_devtree_update(void)
+{
+ /* Override dev tree settings per board */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ mainboard_ec_init();
+
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/puff/romstage.c b/src/mainboard/google/puff/romstage.c
new file mode 100644
index 0000000..7174a8c
--- /dev/null
+++ b/src/mainboard/google/puff/romstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+#include <spd_bin.h>
+
+/*
+ * GPIO_MEM_CH_SEL is set to 1 for single channel skus
+ * and 0 for dual channel skus.
+ */
+//#define GPIO_MEM_CH_SEL GPP_F2
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ struct cnl_mb_cfg memcfg;
+ variant_memory_params(&memcfg);
+
+ /* Read spd block to get memory config */
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52 },
+ };
+
+ memcfg.dq_pins_interleaved = 1;
+ get_spd_smbus(&blk);
+ memcfg.spd[0].read_type = READ_SMBUS;
+ memcfg.spd[0].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[0];
+ memcfg.spd[1].read_type = READ_SMBUS;
+ memcfg.spd[1].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[1];
+ dump_spd_info(&blk);
+
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/google/puff/smihandler.c b/src/mainboard/google/puff/smihandler.c
new file mode 100644
index 0000000..c7833e3
--- /dev/null
+++ b/src/mainboard/google/puff/smihandler.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <baseboard/variants.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_sleep_gpio_table(slp_typ, &num);
+ gpio_configure_pads(pads, num);
+
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S0IX_WAKE_EVENTS);
+}
diff --git a/src/mainboard/google/puff/variants/baseboard/Makefile.inc b/src/mainboard/google/puff/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..5d5695f
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/Makefile.inc
@@ -0,0 +1,25 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+
+verstage-y += gpio.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000..7382209
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -0,0 +1,358 @@
+chip soc/intel/cannonlake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # DW1 is used by:
+ # - GPP_C1 - PCIE_14_WLAN_WAKE_ODL
+ # - GPP_C21 - H1_PCH_INT_ODL
+ register "gpe0_dw0" = "PMC_GPP_A"
+ register "gpe0_dw1" = "PMC_GPP_C"
+ register "gpe0_dw2" = "PMC_GPP_D"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # FSP configuration
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "Sata_AHCI"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ # Configure devslp pad reset to PLT_RST
+ register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset"
+ register "satapwroptimize" = "1"
+ # Enable System Agent dynamic frequency
+ register "SaGv" = "SaGv_Enabled"
+ # Enable heci communication
+ register "HeciEnabled" = "0"
+ # Enable Speed Shift Technology support
+ register "speed_shift_enable" = "1"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+ # Enable DPTF
+ register "dptf_enable" = "1"
+ register "tdp_pl1_override" = "15"
+ register "tdp_pl2_override" = "64"
+ register "Device4Enable" = "1"
+ # Enable eDP device
+ register "DdiPortEdp" = "1"
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ register "tcc_offset" = "10" # TCC of 90C
+ # Unlock GPIO pads
+ register "PchUnlockGpioPads" = "1"
+ # SD card WP pin confguration
+ register "ScsSdCardWpPinEnabled" = "0"
+
+ # NOTE: if any variant wants to override this value, use the same format
+ # as register "common_soc_config.pch_thermal_trip" = "value", instead of
+ # putting it under register "common_soc_config" in overridetree.cb file.
+ register "common_soc_config.pch_thermal_trip" = "77"
+
+ register "PmTimerDisabled" = "1"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 6A | 70A | 31A | 31A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
+ #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
+ #+----------------+-------+-------+-------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(6),
+ .voltage_limit = 1520,
+ .ac_loadline = 1030,
+ .dc_loadline = 1030,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(70),
+ .voltage_limit = 1520,
+ .ac_loadline = 180,
+ .dc_loadline = 180,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ register "PchPmSlpS3MinAssert" = "2" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "1" # 500ms
+ register "PchPmSlpAMinAssert" = "3" # 2s
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
+ register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
+ register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
+ register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+
+ # Enable Root port 9(x4) for NVMe.
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ # RP 9 uses CLK SRC 1
+ register "PcieClkSrcUsage[1]" = "8"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 1
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # PCIe port 14 for M.2 E-key WLAN
+ register "PcieRpEnable[13]" = "1"
+ register "PcieRpLtrEnable[13]" = "1"
+ # RP 14 uses CLK SRC 3
+ register "PcieClkSrcUsage[3]" = "13"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override)
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaAudioLinkSsp0" = "1"
+ register "PchHdaAudioLinkSsp1" = "1"
+ register "PchHdaAudioLinkDmic0" = "1"
+ register "PchHdaAudioLinkDmic1" = "0"
+
+ # GPIO PM programming
+ register "gpio_override_pm" = "1"
+
+ # GPIO community PM configuration
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
+
+ # chipset_lockdown configuration
+ # Use below format to override value in overridetree.cb if required
+ # format:
+ # register "common_soc_config.<variable_name>" = "value"
+ register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 off end # SA Thermal device
+ device pci 05.0 off end # SA IPU
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port 1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port 1""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
+ device usb 2.9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port 1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port 1""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 3.4 on end
+ end
+ end
+ end
+ end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PME_B0"
+ device pci 14.3 on end # CNVi wifi
+ end
+ device pci 14.5 on end # SDCard
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1 (USB)
+ device pci 1c.1 off end # PCI Express Port 2 (USB)
+ device pci 1c.2 off end # PCI Express Port 3 (USB)
+ device pci 1c.3 off end # PCI Express Port 4 (USB)
+ device pci 1c.4 off end # PCI Express Port 5 (USB)
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9 (X4 NVME)
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express port 13
+ device pci 1d.5 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW1_01"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 14 (x4)
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # eSPI Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/puff/variants/baseboard/gpio.c b/src/mainboard/google/puff/variants/baseboard/gpio.c
new file mode 100644
index 0000000..f8df447
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/gpio.c
@@ -0,0 +1,445 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+ /* A0 : SAR0_INT_ODL */
+ PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL),
+ /* A1 : ESPI_IO0 */
+ /* A2 : ESPI_IO1 */
+ /* A3 : ESPI_IO2 */
+ /* A4 : ESPI_IO3 */
+ /* A5 : ESPI_CS# */
+ /* A6 : SAR1_INT_ODL */
+ PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL),
+ /* A7 : PP3300_SOC_A */
+ PAD_NC(GPP_A7, NONE),
+ /* A8 : PEN_GARAGE_DET_L (wake) */
+ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
+ /* A9 : ESPI_CLK */
+ /* A10 : FPMCU_PCH_BOOT1 */
+ PAD_CFG_GPO(GPP_A10, 0, DEEP),
+ /* A11 : PCH_SPI_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
+ /* A12 : FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_A12, 1, DEEP),
+ /* A13 : SUSWARN_L */
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+ /* A14 : ESPI_RST_L */
+ /* A15 : SUSACK_L */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : SD_1P8_SEL => NC */
+ PAD_NC(GPP_A16, NONE),
+ /* A17 : EN_PP3300_SD_DX */
+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+ /* A18 : EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_A18, 1, DEEP),
+ /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
+ PAD_CFG_GPO(GPP_A19, 1, DEEP),
+ /* A20 : WLAN_INT_L */
+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
+ /* A21 : TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT),
+ /* A22 : FPMCU_PCH_BOOT0 */
+ PAD_CFG_GPO(GPP_A22, 0, DEEP),
+ /* A23 : FPMCU_PCH_INT_ODL */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
+
+ /* B0 : CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ /* B1 : CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ /* B2 : GPP_B2 ==> NC */
+ PAD_NC(GPP_B2, NONE),
+ /* B3 : GPP_B3 ==> NC */
+ PAD_NC(GPP_B3, NONE),
+ /* B4 : GPP_B4 ==> NC */
+ PAD_NC(GPP_B4, NONE),
+ /* B5 : GPP_B5 ==> NC */
+ PAD_NC(GPP_B5, NONE),
+ /* B6 : SRCCLKREQ1 */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : GPP_B7 ==> NC */
+ PAD_NC(GPP_B7, NONE),
+ /* B8 : PCIE_14_WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : GPP_B9 ==> NC */
+ PAD_NC(GPP_B9, NONE),
+ /* B10 : GPP_B10 ==> NC */
+ PAD_NC(GPP_B10, NONE),
+ /* B11 : EXT_PWR_GATE_L */
+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+ /* B12 : SLP_S0_L */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLT_RST_L */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : GPP_B14_STRAP */
+ PAD_NC(GPP_B14, NONE),
+ /* B15 : H1_SLAVE_SPI_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : H1_SLAVE_SPI_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : H1_SLAVE_SPI_MISO_R */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : H1_SLAVE_SPI_MOSI_R */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* B20 : PCH_SPI_FPMCU_CLK_R */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* B21 : PCH_SPI_FPMCU_MISO */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+ /* B22 : PCH_SPI_FPMCU_MOSI */
+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+ /* B23 : GPP_B23_STRAP */
+ PAD_NC(GPP_B23, NONE),
+
+ /* C0 : GPP_C0 => NC */
+ PAD_NC(GPP_C0, NONE),
+ /* C1 : PCIE_14_WLAN_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
+ /* C2 : GPP_C2 => NC */
+ PAD_NC(GPP_C2, NONE),
+ /* C3 : WLAN_OFF_L */
+ PAD_CFG_GPO(GPP_C3, 1, DEEP),
+ /* C4 : TOUCHSCREEN_DIS_L */
+ PAD_CFG_GPO(GPP_C4, 1, DEEP),
+ /* C5 : GPP_C5 => NC */
+ PAD_NC(GPP_C5, NONE),
+ /* C6 : PEN_PDCT_OD_L */
+ PAD_NC(GPP_C6, NONE),
+ /* C7 : PEN_IRQ_OD_L */
+ PAD_NC(GPP_C7, NONE),
+ /* C8 : UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+ /* C9 : UART_PCH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+ /* C10 : GPP_10 ==> GPP_C10_TP */
+ PAD_NC(GPP_C10, NONE),
+ /* C11 : GPP_11 ==> EN_FP_RAILS */
+ PAD_CFG_GPO(GPP_C11, 1, DEEP),
+ /* C12 : GPP_C12 ==> NC */
+ PAD_NC(GPP_C12, NONE),
+ /* C13 : EC_PCH_INT_L */
+ PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
+ /* C14 : BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_C14, 1, DEEP),
+ /* C15 : WWAN_DPR_SAR_ODL
+ *
+ * TODO: Driver doesn't use this pin as of now. In case driver starts
+ * using this pin, expose this pin to driver.
+ */
+ PAD_CFG_GPO(GPP_C15, 1, DEEP),
+ /* C16 : PCH_I2C_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : PCH_I2C_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : PCH_I2C_TOUCHSCREEN_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : PCH_I2C_TOUCHSCREEN_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : PCH_WP_OD */
+ PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ /* C21 : H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C22 : EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+ /* C23 : WLAN_PE_RST# */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+ /* D0 : TP31 */
+ PAD_NC(GPP_D0, NONE),
+ /* D1 : TP16 */
+ PAD_NC(GPP_D1, NONE),
+ /* D2 : TP26 */
+ PAD_NC(GPP_D2, NONE),
+ /* D3 : TP27 */
+ PAD_NC(GPP_D3, NONE),
+ /* D4 : TP40 */
+ PAD_NC(GPP_D4, NONE),
+ /* D5 : WWAN_CONFIG_0 */
+ PAD_NC(GPP_D5, NONE),
+ /* D6 : WWAN_CONFIG_1 */
+ PAD_NC(GPP_D6, NONE),
+ /* D7 : WWAN_CONFIG_2 */
+ PAD_NC(GPP_D7, NONE),
+ /* D8 : WWAN_CONFIG_3 */
+ PAD_NC(GPP_D8, NONE),
+ /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_D9, 0, DEEP),
+ /* D10 : GPP_D10 ==> NC */
+ PAD_NC(GPP_D10, NONE),
+ /* D11 : GPP_D11 ==> NC */
+ PAD_NC(GPP_D11, NONE),
+ /* D12 : GPP_D12 */
+ PAD_NC(GPP_D12, NONE),
+ /* D13 : ISH_UART_RX */
+ PAD_NC(GPP_D13, NONE),
+ /* D14 : ISH_UART_TX */
+ PAD_NC(GPP_D14, NONE),
+ /* D15 : TOUCHSCREEN_RST_L */
+ PAD_CFG_GPO(GPP_D15, 0, DEEP),
+ /* D16 : USI_INT */
+ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE),
+ /* D17 : PCH_HP_SDW_CLK */
+ PAD_NC(GPP_D17, NONE),
+ /* D18 : PCH_HP_SDW_DAT */
+ PAD_NC(GPP_D18, NONE),
+ /* D19 : DMIC_CLK_0_SNDW4_CLK */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* D20 : DMIC_DATA_0_SNDW4_DATA */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+ /* D21 : GPP_D21 ==> NC */
+ PAD_NC(GPP_D21, NONE),
+ /* D22 : GPP_D22 ==> NC */
+ PAD_NC(GPP_D22, NONE),
+ /* D23 : SPP_MCLK */
+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+ /* E0 : GPP_E0 ==> NC */
+ PAD_NC(GPP_E0, NONE),
+ /* E1 : M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+ /* E2 : GPP_E2 ==> NC */
+ PAD_NC(GPP_E2, NONE),
+ /* E3 : GPP_E3 ==> NC */
+ PAD_NC(GPP_E3, NONE),
+ /* E4 : M2_SSD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+ /* E5 : SATA_DEVSLP1 */
+ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+ /* E6 : M2_SSD_RST_L */
+ PAD_NC(GPP_E6, NONE),
+ /* E7 : GPP_E7 ==> NC */
+ PAD_NC(GPP_E7, NONE),
+ /* E8 : GPP_E8 ==> NC */
+ PAD_NC(GPP_E8, NONE),
+ /* E9 : GPP_E9 ==> NC */
+ PAD_NC(GPP_E9, NONE),
+ /* E10 : GPP_E10 ==> NC */
+ PAD_NC(GPP_E10, NONE),
+ /* E11 : USB_C_OC_OD USB_OC2 */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+ /* E12 : USB_A_OC_OD USB_OC3 */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+ /* E13 : USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+ /* E14 : DDI2_HPD_ODL */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* E15 : DDPD_HPD2 => NC */
+ PAD_NC(GPP_E15, NONE),
+ /* E16 : DDPE_HPD2 => NC */
+ PAD_NC(GPP_E16, NONE),
+ /* E17 : EDP_HPD */
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+ /* E18 : DDPB_CTRLCLK => NC */
+ PAD_NC(GPP_E18, NONE),
+ /* E19 : GPP_E19_STRAP */
+ PAD_CFG_GPI(GPP_E19, NONE, DEEP),
+ /* E20 : DDPC_CTRLCLK => NC */
+ PAD_NC(GPP_E20, NONE),
+ /* E21 : GPP_E21_STRAP */
+ PAD_CFG_GPI(GPP_E21, NONE, DEEP),
+ /* E22 : DDPD_CTRLCLK => NC */
+ PAD_NC(GPP_E22, NONE),
+ /* E23 : GPP_E23_STRAP */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F0 : GPIO_WWAN_WLAN_COEX3 */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ /* F1 : WWAN_RESET_1V8_ODL */
+ PAD_CFG_GPO(GPP_F1, 1, DEEP),
+ /* F2 : MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
+ /* F3 : GPP_F3 ==> NC */
+ PAD_NC(GPP_F3, NONE),
+ /* F4 : CNV_BRI_DT */
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : CNV_BRI_RSP */
+ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+ /* F6 : CNV_RGI_DT */
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+ /* F7 : CNV_RGI_RSP */
+ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+ /* F8 : UART_WWANTX_WLANRX_COEX1 */
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+ /* F9 : UART_WWANRX_WLANTX_COEX2 */
+ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+ /* F10 : GPP_F10 ==> NC */
+ PAD_NC(GPP_F10, NONE),
+ /* F11 : PCH_MEM_STRAP2 */
+ PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
+ /* F12 : GPP_F12 ==> NC */
+ PAD_NC(GPP_F12, NONE),
+ /* F13 : GPP_F13 ==> NC */
+ PAD_NC(GPP_F13, NONE),
+ /* F14 : GPP_F14 ==> NC */
+ PAD_NC(GPP_F14, NONE),
+ /* F15 : GPP_F15 ==> NC */
+ PAD_NC(GPP_F15, NONE),
+ /* F16 : GPP_F16 ==> NC */
+ PAD_NC(GPP_F16, NONE),
+ /* F17 : GPP_F17 ==> NC */
+ PAD_NC(GPP_F17, NONE),
+ /* F18 : GPP_F18 ==> NC */
+ PAD_NC(GPP_F18, NONE),
+ /* F19 : GPP_F19 ==> NC */
+ PAD_NC(GPP_F19, NONE),
+ /* F20 : PCH_MEM_STRAP0 */
+ PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
+ /* F21 : PCH_MEM_STRAP1 */
+ PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
+ /* F22 : PCH_MEM_STRAP3 */
+ PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
+ /* F23 : GPP_F23 ==> NC */
+ PAD_NC(GPP_F23, NONE),
+
+ /* G0 : SD_CMD */
+ PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
+ /* G1 : SD_DATA0 */
+ PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
+ /* G2 : SD_DATA1 */
+ PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
+ /* G3 : SD_DATA2 */
+ PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
+ /* G4 : SD_DATA3 */
+ PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
+ /* G5 : SD_CD# */
+ PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
+ /* G6 : SD_CLK */
+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+ /* G7 : SD_WP
+ * As per schematics SD host controller SD_WP pin is not connected to
+ * uSD card connector. In order to overcome gpio default state, ensures
+ * to configure gpio pin as NF1 with internal 20K pull down.
+ */
+ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
+ /*
+ * H0 : HP_INT_L
+ */
+ PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH),
+ /* H1 : CNV_RF_RESET_L */
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
+ /* H2 : CNV_CLKREQ0 */
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+ /* H3 : SPKR_PA_EN */
+ PAD_CFG_GPO(GPP_H3, 0, DEEP),
+ /* H4 : PCH_I2C_PEN_SDA */
+ PAD_NC(GPP_H4, NONE),
+ /* H5 : PCH_I2C_PEN_SCL */
+ PAD_NC(GPP_H5, NONE),
+ /* H6 : PCH_I2C_SAR0_MST_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : PCH_I2C_SAR0_MST_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+ /* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+ /* H10 : PCH_I2C_TRACKPAD_SDA */
+ PAD_NC(GPP_H10, NONE),
+ /* H11 : PCH_I2C_TRACKPAD_SCL */
+ PAD_NC(GPP_H11, NONE),
+ /* H12 : GPP_H12 ==> NC */
+ PAD_NC(GPP_H12, NONE),
+ /* H13 : GPP_H13 ==> NC */
+ PAD_NC(GPP_H13, NONE),
+ /* H14 : GPP_H14 ==> NC */
+ PAD_NC(GPP_H14, NONE),
+ /* H15 : GPP_H15 ==> NC */
+ PAD_NC(GPP_H15, NONE),
+ /* H16 : GPP_H16 ==> NC */
+ PAD_NC(GPP_H16, NONE),
+ /* H17 : TP1 */
+ PAD_NC(GPP_H17, NONE),
+ /* H18 : CPU_C10_GATE_L */
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+ /* H19 : GPP_H19 ==> NC */
+ PAD_NC(GPP_H19, NONE),
+ /* H20 : TP41 */
+ PAD_NC(GPP_H20, NONE),
+ /* H21 : XTAL_FREQ_SEL */
+ PAD_NC(GPP_H21, NONE),
+ /* H22 : GPP_H22 ==> NC */
+ PAD_NC(GPP_H22, NONE),
+ /* H23 : GPP_H23_STRAP */
+ PAD_NC(GPP_H23, NONE),
+
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+
+ /* SD card detect VGPIO */
+ PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
+
+ /* CNV_WCEN : Disable Wireless Charging */
+ PAD_CFG_GPO(CNV_WCEN, 0, DEEP),
+};
+
+const struct pad_config *base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/*
+ * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
+ * as GPO before entering sleep.
+ */
+static const struct pad_config default_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
+};
+
+/*
+ * GPIO settings before entering S5, which are same as
+ * default_sleep_gpio_table but also,
+ * turn off EN_PP3300_WWAN.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
+};
+
+const struct pad_config *__weak variant_sleep_gpio_table(
+ u8 slp_typ, size_t *num)
+{
+ if (slp_typ == ACPI_S5) {
+ *num = ARRAY_SIZE(s5_sleep_gpio_table);
+ return s5_sleep_gpio_table;
+ }
+ *num = ARRAY_SIZE(default_sleep_gpio_table);
+ return default_sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
+
+/* Weak implementation of overrides */
+const struct pad_config *__weak override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 0000000..b18932e
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+#define DPTF_CPU_ACTIVE_AC0 87
+#define DPTF_CPU_ACTIVE_AC1 85
+#define DPTF_CPU_ACTIVE_AC2 83
+#define DPTF_CPU_ACTIVE_AC3 80
+#define DPTF_CPU_ACTIVE_AC4 75
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE 65
+#define DPTF_TSR0_CRITICAL 75
+#define DPTF_TSR0_ACTIVE_AC0 50
+#define DPTF_TSR0_ACTIVE_AC1 47
+#define DPTF_TSR0_ACTIVE_AC2 45
+#define DPTF_TSR0_ACTIVE_AC3 42
+#define DPTF_TSR0_ACTIVE_AC4 39
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE 65
+#define DPTF_TSR1_CRITICAL 75
+#define DPTF_TSR1_ACTIVE_AC0 50
+#define DPTF_TSR1_ACTIVE_AC1 47
+#define DPTF_TSR1_ACTIVE_AC2 45
+#define DPTF_TSR1_ACTIVE_AC3 42
+#define DPTF_TSR1_ACTIVE_AC4 39
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO : Need to update this Table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
+ Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
+ Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
+ Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
+ Package () {50, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {40, 0xFFFFFFFF, 2904, 55, 550},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ }
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on Ambient (TSR0) */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on Charger (TSR1) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 64000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..3aa9414
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+ (MAINBOARD_EC_S3_WAKE_EVENTS | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..e83732c
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+#define GPIO_EC_IN_RW GPP_C22
+
+#define GPIO_PCH_WP GPP_C20
+
+/* EC wake pin is LAN_WAKE# */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* EC sync irq is GPP_C13_IRQ */
+#define EC_SYNC_IRQ GPP_C13_IRQ
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..920e428
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table. The "base" GPIOs live in the "baseboard" variant, and
+ * the overrides live with the specific board (kohaku, kled, etc.).
+*/
+const struct pad_config *base_gpio_table(size_t *num);
+const struct pad_config *override_gpio_table(size_t *num);
+
+/* Return board specific memory configuration */
+void variant_memory_params(struct cnl_mb_cfg *bcfg);
+
+/* Return memory SKU for the variant */
+int variant_memory_sku(void);
+
+/* Return variant specific gpio pads to be configured during sleep */
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num);
+
+/* Return GPIO pads that need to be configured before ramstage */
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Return board SKU */
+uint32_t get_board_sku(void);
+
+/* Modify devictree settings during ramstage. */
+void variant_devtree_update(void);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/puff/variants/baseboard/memory.c b/src/mainboard/google/puff/variants/baseboard/memory.c
new file mode 100644
index 0000000..bcfc49f
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/memory.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <soc/cnl_memcfg_init.h>
+#include <string.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+ /* Baseboard uses 121, 81 and 100 rcomp resistors */
+ .rcomp_resistor = {121, 81, 100},
+
+ /* Baseboard Rcomp target values */
+ .rcomp_targets = {100, 40, 20, 20, 26},
+
+ /* Set CaVref config to 2 */
+ .vref_ca_config = 2,
+
+ /* Enable Early Command Training */
+ .ect = 1,
+};
+
+void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
+{
+ memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
+}
diff --git a/src/mainboard/google/puff/variants/puff/Makefile.inc b/src/mainboard/google/puff/variants/puff/Makefile.inc
new file mode 100644
index 0000000..30daaf7
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/Makefile.inc
@@ -0,0 +1,16 @@
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += gpio.c
+bootblock-y += gpio.c
diff --git a/src/mainboard/google/puff/variants/puff/gpio.c b/src/mainboard/google/puff/variants/puff/gpio.c
new file mode 100644
index 0000000..f3efae5
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/gpio.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..31f72b3
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/puff/variants/puff/include/variant/ec.h b/src/mainboard/google/puff/variants/puff/include/variant/ec.h
new file mode 100644
index 0000000..c36f957
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/puff/variants/puff/include/variant/gpio.h b/src/mainboard/google/puff/variants/puff/include/variant/gpio.h
new file mode 100644
index 0000000..5d69eed
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb
new file mode 100644
index 0000000..bc6aa11
--- /dev/null
+++ b/src/mainboard/google/puff/variants/puff/overridetree.cb
@@ -0,0 +1,181 @@
+chip soc/intel/cannonlake
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | FP MCU |
+ #| I2C0 | Touchpad |
+ #| I2C1 | Touch screen |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 50,
+ .fall_time_ns = 15,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 60,
+ .fall_time_ns = 25,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 150,
+ .fall_time_ns = 150,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 120,
+ .fall_time_ns = 120,
+ },
+ }"
+
+ # GPIO for SD card detect
+ register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+ device domain 0 on
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+ register "wake" = "GPE0_DW0_21"
+ device i2c 15 on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "reset_delay_ms" = "100"
+ register "reset_off_delay_ms" = "5"
+ register "has_power_resource" = "1"
+ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+ register "stop_off_delay_ms" = "5"
+ device i2c 49 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GDIX0000""
+ register "generic.desc" = ""Goodix Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "generic.reset_delay_ms" = "500"
+ register "generic.reset_off_delay_ms" = "3"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+ register "generic.enable_delay_ms" = "12"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 5d on end
+ end
+ chip drivers/generic/gpio_keys
+ register "name" = ""PENH""
+ register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
+ register "key.wake" = "GPE0_DW0_08"
+ register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+ register "key.dev_name" = ""EJCT""
+ register "key.linux_code" = "SW_PEN_INSERTED"
+ register "key.linux_input_type" = "EV_SW"
+ register "key.label" = ""pen_eject""
+ device generic 0 on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 on
+ chip drivers/i2c/sx9310
+ register "desc" = ""SAR Proximity Sensor""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
+ register "speed" = "I2C_SPEED_FAST"
+ register "uid" = "1"
+ register "reg_prox_ctrl0" = "0x10"
+ register "reg_prox_ctrl1" = "0x00"
+ register "reg_prox_ctrl2" = "0x84"
+ register "reg_prox_ctrl3" = "0x0e"
+ register "reg_prox_ctrl4" = "0x07"
+ register "reg_prox_ctrl5" = "0xc6"
+ register "reg_prox_ctrl6" = "0x20"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
+ register "reg_prox_ctrl9" = "0x43"
+ register "reg_prox_ctrl10" = "0x1f"
+ register "reg_prox_ctrl11" = "0x00"
+ register "reg_prox_ctrl12" = "0x00"
+ register "reg_prox_ctrl13" = "0x00"
+ register "reg_prox_ctrl14" = "0x00"
+ register "reg_prox_ctrl15" = "0x00"
+ register "reg_prox_ctrl16" = "0x00"
+ register "reg_prox_ctrl17" = "0x00"
+ register "reg_prox_ctrl18" = "0x00"
+ register "reg_prox_ctrl19" = "0x00"
+ register "reg_sar_ctrl0" = "0x50"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
+ device i2c 28 on end
+ end
+ end # I2C #3
+ device pci 19.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+ register "property_count" = "1"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end #I2C #4
+ device pci 1e.3 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
+ device spi 1 on end
+ end # FPMCU
+ end # GSPI #1
+ end
+
+end
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