Subrata Banik uploaded patch set #3 to the change originally created by Subrata Banik.

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apollolake boards: Enable CSE in devicetree

Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.

Calling me_read_config32(offset) function from ramstage:

Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
---
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
14 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45469/3

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