Karthik Ramasubramanian has uploaded this change for review.
soc/intel/jasperlake: Allow mainboard to override chip configuration
Add a weak override function to allow mainboard to override chip
configuration like GPIO PM.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that the suspend/resume
sequence works fine.
Change-Id: I40fa655b0324dc444182b988f0089587e3877a47
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
---
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/jasperlake/include/soc/ramstage.h
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45856/1
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index cdd088e..d140213 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -78,6 +78,11 @@
sizeof(config->SerialIoUartMode));
}
+__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config)
+{
+ /* Override settings per board. */
+}
+
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
@@ -86,6 +91,9 @@
FSP_S_CONFIG *params = &supd->FspsConfig;
struct soc_intel_jasperlake_config *config = config_of_soc();
+ /* Allow mainboard to override any chip config */
+ mainboard_update_soc_chip_config(config);
+
/* Parse device tree and fill in FSP UPDs */
parse_devicetree(params);
diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h
index 8188fbd..1de8e37 100644
--- a/src/soc/intel/jasperlake/include/soc/ramstage.h
+++ b/src/soc/intel/jasperlake/include/soc/ramstage.h
@@ -9,6 +9,7 @@
#include <soc/soc_chip.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config);
void soc_init_pre_device(void *chip_info);
#endif
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