[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge: Correct bugs in lpc.c

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32551 )

Change subject: soc/amd/stoneyridge: Correct bugs in lpc.c
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/32551/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/32551/1//COMMIT_MSG@12 
PS1, Line 12: Since the bridge is enabled in bootblock to allow port 80h,
            : there is no need to maintain it in ramstage.
I'm ok with that for Stoney, although adding a comment to that effect would probably be good.
For Picasso, are we just going to assume that the ABL has already enabled it?