[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )

Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage
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Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36087/15//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36087/15//COMMIT_MSG@22 
PS15, Line 22:
> Subrata, there are a number of patchsets here. […]

Yes Furquan, this list is valid but its till yesterday, so what i will do after ICL https://review.coreboot.org/c/coreboot/+/36627 CL +2 and merge, i will rebase this entire patch tree (4 CL) and make it ready. consideration is anything changes in ICL or common part, i need to rebase everytime.