1 comment:
File src/soc/intel/tigerlake/include/soc/iomap.h:
Patch Set #3, Line 79: #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
TGL supports 512GiB of address space (39 bits). So size should really be 512GiB - TOUUD.
I was actually wondering about the same thing. How are all these sizes calculated and why are they static? Currently, these are used to set the total size of high MMIO:
gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
which seems wrong.. Shouldn't this be:
gnvs->a4gs = cpu_phys_address_size() - gnvs->a4gb;?
To view, visit change 41155. To unsubscribe, or for help writing mail filters, visit settings.