Lean Sheng Tan submitted this change.

View Change

Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
sb/intel/bd82x6x/sata: Enable SATA clock gating

Program SATA IOBP and enable clock gating after port enable
bits have been written.

The same registers are already set for DMI and PCIe.

TEST: Lenovo X220 still boots over SATA.

Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/southbridge/intel/bd82x6x/sata.c
1 file changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 9dc58fd..a30c01a 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -219,6 +219,10 @@
~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3),
1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 |
1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3);
+
+ /* SATA clock gating. Must be done after writing register 0x94. */
+ pch_iobp_update(0xEA007F07, ~0U, (1 << 31));
+ pch_iobp_update(0xEA004000, ~0U, (1 << 7));
}

static void sata_enable(struct device *dev)

To view, visit change 79146. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Gerrit-Change-Number: 79146
Gerrit-PatchSet: 4
Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan@9elements.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged