Dan Elkouby has uploaded this change for review.
cpu/intel/model_206ax: detect number of MCE banks
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset
only 7. This causes Linux to spuriously log errors during boot and S3
resume.
Fix this by reading the real value from the right MSR.
Change-Id: Id05645009259fd77b4de49bde518361eeae46617
---
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
2 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28443/1
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 7cb4069..98203b6 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -39,6 +39,7 @@
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
+#define IA32_MCG_CAP 0x179
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 75631c1..3cc8d82 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -414,10 +414,14 @@
{
msr_t msr;
int i;
+ int num_banks;
+
+ msr = rdmsr(IA32_MCG_CAP);
+ num_banks = msr.lo & 0xff;
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
- for (i = 0; i < 7; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
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