HAOUAS Elyes has uploaded this change for review.
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/cpu/amd/agesa/family14/fixme.c
M src/mainboard/asrock/e350m1/acpi/routing.asl
M src/mainboard/asus/f2a85-m/acpi/routing.asl
M src/mainboard/gizmosphere/gizmo/acpi/routing.asl
M src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl
M src/mainboard/lenovo/g505s/acpi/routing.asl
M src/mainboard/msi/ms7721/acpi/routing.asl
M src/mainboard/pcengines/apu1/acpi/routing.asl
M src/soc/intel/baytrail/acpi/globalnvs.asl
M src/soc/intel/baytrail/include/soc/nvs.h
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/braswell/acpi/globalnvs.asl
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/broadwell/acpi/globalnvs.asl
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/denverton_ns/smm.c
M src/soc/intel/icelake/chip.h
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/tigerlake/chip.h
M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
M src/southbridge/intel/bd82x6x/nvs.h
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/ibexpeak/nvs.h
M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
M src/southbridge/intel/lynxpoint/nvs.h
28 files changed, 30 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39101/1
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index be7c635..658434d 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -100,7 +100,7 @@
PciValue |= 0x80000000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- /* Initialize GMM Base Address for Pcie Mode
+ /* Initialize GMM Base Address for PCIe Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
@@ -112,7 +112,7 @@
PciValue |= 0x96000000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- /* Initialize FB Base Address for Pcie Mode
+ /* Initialize FB Base Address for PCIe Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl
index 537bcac..0675012 100644
--- a/src/mainboard/asrock/e350m1/acpi/routing.asl
+++ b/src/mainboard/asrock/e350m1/acpi/routing.asl
@@ -199,7 +199,7 @@
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
- /* TODO: pcie */
+ /* TODO: PCIe */
Package(){0x0015FFFF, 0, 0, 16 },
Package(){0x0015FFFF, 1, 0, 17 },
Package(){0x0015FFFF, 2, 0, 18 },
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index c0aef87..38ba142 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -78,7 +78,7 @@
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
- /* Bus 0, Dev 21 Pcie Bridge */
+ /* Bus 0, Dev 21 PCIe Bridge */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl
index 447d992..af05ec6 100644
--- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl
+++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl
@@ -200,7 +200,7 @@
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
- /* TODO: pcie */
+ /* TODO: PCIe */
Package(){0x0015FFFF, 0, 0, 16 },
Package(){0x0015FFFF, 1, 0, 17 },
Package(){0x0015FFFF, 2, 0, 18 },
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl
index 22c4550..a1ce860 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl
+++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl
@@ -90,7 +90,7 @@
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
- /* Bus 0, Dev 21 Pcie Bridge */
+ /* Bus 0, Dev 21 PCIe Bridge */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl
index 22c4550..a1ce860 100644
--- a/src/mainboard/lenovo/g505s/acpi/routing.asl
+++ b/src/mainboard/lenovo/g505s/acpi/routing.asl
@@ -90,7 +90,7 @@
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
- /* Bus 0, Dev 21 Pcie Bridge */
+ /* Bus 0, Dev 21 PCIe Bridge */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl
index 0af6b42..5443dd5 100644
--- a/src/mainboard/msi/ms7721/acpi/routing.asl
+++ b/src/mainboard/msi/ms7721/acpi/routing.asl
@@ -71,7 +71,7 @@
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
- /* Bus 0, Dev 21 Pcie Bridge */
+ /* Bus 0, Dev 21 PCIe Bridge */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl
index 9a63d72..79ebef3 100644
--- a/src/mainboard/pcengines/apu1/acpi/routing.asl
+++ b/src/mainboard/pcengines/apu1/acpi/routing.asl
@@ -162,7 +162,7 @@
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
- /* TODO: pcie */
+ /* TODO: PCIe */
Package(){0x0015FFFF, 0, 0, 16 },
Package(){0x0015FFFF, 1, 0, 17 },
Package(){0x0015FFFF, 2, 0, 18 },
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index f33fcf6..4764931 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -99,7 +99,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 4a89eb9..8532728 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -83,7 +83,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 6dc0346..6b6c28d 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -163,7 +163,7 @@
dev->path.pci.devfn &= ~0x7;
dev->path.pci.devfn |= func;
- /* is pcie device there */
+ /* is PCIe device there */
if (pci_read_config32(dev, 0) == 0xFFFFFFFF)
continue;
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 9bd9afc..70b83be 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -101,7 +101,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 33800ef..f4cd8f2 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -86,7 +86,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index 9ceeca5..1508b06 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -91,7 +91,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 456fda6..ea64341 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -75,7 +75,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd2; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index fd37d26..a7ad07e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -180,7 +180,7 @@
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
- /* PCIe output clocks type to Pcie devices.
+ /* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index d05e76b..75f179e 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -53,7 +53,7 @@
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events Disable pcie wake. */
+ /* Configure events Disable PCIe wake. */
enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 0687513..e82bec0 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -134,7 +134,7 @@
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
- /* PCIe output clocks type to Pcie devices.
+ /* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index b2467f9..372f527 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -106,7 +106,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b189a16..2c3d3a5 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -226,7 +226,7 @@
u8 PchDciEn;
/*
- * Pcie Root Port configuration:
+ * PCIe Root Port configuration:
* each element of array corresponds to
* respective PCIe root port.
*/
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index d5f62f6..24e4cf1 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -88,7 +88,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 75a399f..8176b07 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -114,7 +114,7 @@
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
- /* PCIe output clocks type to Pcie devices.
+ /* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index f7652ee..3983962 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -166,7 +166,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index a6b0bdb..0ec0c05 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -138,7 +138,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 5c2b130..7c672b3 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -351,8 +351,8 @@
* If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
* If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
*
- * This check is done here instead of pcie driver
- * because the pcie driver enable() handler is not
+ * This check is done here instead of PCIe driver
+ * because the PCIe driver enable() handler is not
* called unless the device is enabled.
*/
if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index a956398..a0422f2 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -137,7 +137,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index ba9f850..fc8e219 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -161,7 +161,7 @@
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index 3aca7bb..34c2537 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -114,7 +114,7 @@
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
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