Xiang Wang has uploaded this change for review.
riscv: separately define stack locations at different stages
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begin
execution will enable cache, then CAR will disappear. So the
Stack will be separated.
Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782
Signed-off-by: Xiang Wang <wxjstz@126.com>
---
M src/arch/riscv/include/arch/memlayout.h
M src/soc/sifive/fu540/include/soc/memlayout.ld
2 files changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28383/1
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
index 9097cf5..bbd0231 100644
--- a/src/arch/riscv/include/arch/memlayout.h
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -20,6 +20,18 @@
#define STACK(addr, size) REGION(stack, addr, size, 4096)
+#if ENV_BOOTBLOCK || ENV_ROMSTAGE
+# define CAR_STACK(addr, size) REGION(stack, addr, size, 4096)
+#else
+# define CAR_STACK(addr, size)
+#endif
+
+#if ENV_RAMSTAGE
+# define MEM_STACK(addr, size) REGION(stack, addr, size, 4096)
+#else
+# define MEM_STACK(addr, size)
+#endif
+
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
index a03c03d..b9b9c47 100644
--- a/src/soc/sifive/fu540/include/soc/memlayout.ld
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -25,11 +25,12 @@
{
L2LIM_START(FU540_L2LIM)
BOOTBLOCK(FU540_L2LIM, 64K)
- STACK(FU540_L2LIM + 64K, 4K)
- PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)
+ CAR_STACK(FU540_L2LIM + 64K, 20K)
+ PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
L2LIM_END(FU540_L2LIM + 2M)
DRAM_START(FU540_DRAM)
RAMSTAGE(FU540_DRAM, 256K)
+ MEM_STACK(FU540_DRAM + 256K, 20K)
}
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