Shuo Liu has uploaded this change for review.
soc/intel/xeon_sp: Reserve FSP MMIO high window
Xeon-SP supports MMIO high window, a.k.a. MMIO window above 4G.
FSP will assign MMIO high ranges to domains, but there will be
unallocated parts among the allocations reserved for non-domain
usage, which will cause segmentation in MTRR UC coverage.
Reserve MMIO high as a whole under domain0/00:0.0. During MTRR
calculation, the MMIO high reservation will connect the
discontinued the domain MMIO64 ranges together to form one
continuous range.
The benefit is to save MTRR usage, which is especially important
on systems with 2 or more sockets, where each socket has multiple
domains.
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
---
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
6 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83538/1
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 3472d58..aac5589 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -141,3 +141,8 @@
{
return 0;
}
+
+bool get_mmio_high_base_size(resource_t *base, resource_t *size)
+{
+ return false;
+}
diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c
index a65e5fc..7ea65c2 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_util.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_util.c
@@ -148,3 +148,8 @@
{
return true;
}
+
+bool get_mmio_high_base_size(resource_t *base, resource_t *size)
+{
+ return false;
+}
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index e694af3..a7b98f3 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -31,4 +31,6 @@
union p2sb_bdf soc_get_hpet_bdf(void);
union p2sb_bdf soc_get_ioapic_bdf(void);
+bool get_mmio_high_base_size(resource_t *base, resource_t *size);
+
#endif
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 0ccacfb..0938260 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -214,3 +214,8 @@
{
return 0;
}
+
+bool get_mmio_high_base_size(resource_t *base, resource_t *size)
+{
+ return false;
+}
diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c
index 5845327..6dd06ac 100644
--- a/src/soc/intel/xeon_sp/spr/soc_util.c
+++ b/src/soc/intel/xeon_sp/spr/soc_util.c
@@ -188,3 +188,12 @@
*/
return (mem_type < MemTypeCxlAccVolatileMem);
}
+
+bool get_mmio_high_base_size(resource_t *base, resource_t *size)
+{
+ const IIO_UDS *hob = get_iio_uds();
+ *base = hob->PlatformData.PlatGlobalMmio64Base;
+ *size = hob->PlatformData.PlatGlobalMmio64Limit - (*base) + 1;
+
+ return true;
+}
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 2e5023d..ecdc054 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -362,13 +362,31 @@
mc_add_dram_resources(dev, &index);
}
+static void mmapvtd_set_resources(struct device *dev)
+{
+ /*
+ * Add MMIO high window.
+ */
+ if (is_domain0(dev->upstream->dev)) {
+ resource_t mmio64_base, mmio64_size;
+ if (get_mmio_high_base_size(&mmio64_base, &mmio64_size)) {
+ int index = 0;
+ for (struct resource *res = dev->resource_list; res; res = res->next)
+ index++;
+ fixed_mem_range_flags(dev, index, mmio64_base, mmio64_size, IORESOURCE_STORED);
+ }
+ }
+
+ pci_dev_set_resources(dev);
+}
+
static void mmapvtd_init(struct device *dev)
{
}
static struct device_operations mmapvtd_ops = {
.read_resources = mmapvtd_read_resources,
- .set_resources = pci_dev_set_resources,
+ .set_resources = mmapvtd_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = mmapvtd_init,
.ops_pci = &soc_pci_ops,
To view, visit change 83538. To unsubscribe, or for help writing mail filters, visit settings.