65 comments:
Patch Set #4, Line 9: Set numerous pads to PAD_NC as per board schematics (they are either NC, or
please wrap at 72 characters
Done
File src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c:
drop or replace by NC; also for all other nc pads
Done
Patch Set #3, Line 47: PAD_NC(GPP_A12, UP_20K),
ack
Done
Patch Set #3, Line 50: PAD_CFG_GPO(GPP_A13, 1, PLTRST),
nc, none
Done
Patch Set #3, Line 56: PAD_CFG_GPO(GPP_A15, 1, PLTRST),
nc, none
Done
Patch Set #3, Line 62: PAD_CFG_GPO(GPP_A17, 1, PLTRST),
nc, 20 up
Done
Patch Set #3, Line 91: PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),
nc, up 20
Done
Patch Set #3, Line 94: PAD_CFG_GPO(GPP_B3, 1, PLTRST),
nc, none
Done
Patch Set #3, Line 97: PAD_CFG_GPO(GPP_B4, 1, DEEP),
nc, none
Done
/* GPP_B6 - GPIO */
PAD_NC(GPP_B6, NONE),
/* GPP_B7 - GPIO */
PAD_NC(GPP_B7, NONE),
/* GPP_B8 - GPIO */
PAD_NC(GPP_B8, NONE),
/* GPP_B9 - GPIO */
PAD_NC(GPP_B9, NONE),
GPP_B9 should be nc, none - since LAN1_CLK_REQ goes to LAN2 which is not populated
Done; see CB:47220
Patch Set #3, Line 115: PAD_NC(GPP_B10, NONE),
nc, none
Done
Patch Set #3, Line 127: PAD_CFG_GPO(GPP_B14, 1, PLTRST),
separate commit: […]
Done; see CB:47220
/* GPP_B17 - GSPI0_MISO */
PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1),
/* GPP_B18 - GSPI0_MOSI */
PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
/* GPP_B19 - GSPI1_CS0# */
PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1),
/* GPP_B20 - GSPI1_CLK */
PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1),
/* GPP_B21 - GSPI1_MISO */
PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1),
nc, none
Done
Patch Set #3, Line 151: PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1),
nc, 20 up
Done
Patch Set #3, Line 154: PAD_CFG_GPO(GPP_B23, 1, DEEP),
nc, 20 up
Done
Patch Set #3, Line 159: PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK),
nc, 20 up
Done
/* GPP_G2 - GPIO */
PAD_NC(GPP_G2, NONE),
/* GPP_G3 - GPIO */
PAD_NC(GPP_G3, NONE),
/* GPP_G4 - GPIO */
PAD_NC(GPP_G4, NONE),
nc, 20 up
Done
* GPP_G6 - GPIO */
PAD_NC(GPP_G6, NONE),
nc, 20 up
Done
/* GPP_D0 - GPIO */
PAD_NC(GPP_D0, NONE),
/* GPP_D1 - GPIO */
PAD_NC(GPP_D1, NONE),
/* GPP_D2 - GPIO */
PAD_NC(GPP_D2, NONE),
/* GPP_D3 - GPIO */
PAD_NC(GPP_D3, NONE),
/* GPP_D4 - GPIO */
PAD_NC(GPP_D4, NONE),
nc, 20 up
Done
* GPP_D5 - ISH_I2C0_SDA */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* GPP_D6 - ISH_I2C0_SCL */
PAD_CFG_NF(GPP_D6, NONE, DEE
nc, none
Done
/* GPP_D7 - GPIO */
PAD_CFG_GPO(GPP_D7
nc, 20 up
Done
/* GPP_D9 - GPIO */
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
/* GPP_D10 - GPIO */
PAD_CFG_GPO(GPP_D10, 1, PLTRST),
nc, none
Done
/* GPP_D11 - GPIO */
PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP),
/* GPP_D12 - GPIO */
PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE),
nc, 20 up
Done
/* GPP_D15 - GPIO */
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
/* GPP_D16 - GPIO */
PAD_CFG_GPO(GPP_D16, 0, RSMRST),
nc, up 20
Done
/* GPP_D17 - DMIC_CLK1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* GPP_D18 - DMIC_DATA1 */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* GPP_D19 - DMIC_CLK0 */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* GPP_D20 - DMIC_DATA0 */
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
nc, none
Done
/* GPP_D21 - GPIO */
PAD_NC(GPP_D21, NONE),
/* GPP_D22 - GPIO */
PAD_NC(GPP_D22, NONE),
/* GPP_D23 - GPIO */
PAD_NC(GPP_D23, NONE),
nc, 20 up
Done
/* GPP_F0 - GPIO */
PAD_NC(GPP_F0, NONE),
/* GPP_F1 - GPIO */
PAD_CFG_GPO(GPP_F1, 0, RSMRST),
/* GPP_F2 - GPIO */
PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
nc, 20 up
Done
/* GPP_F4 - CNV_BRI_DT */
PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
/* GPP_F5 - CNV_BRI_RSP */
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
nc, 20 up
Done
/* GPP_F6 - CNV_RGI_DT */
PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
/* GPP_F7 - CNV_RGI_RSP */
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
nc, none
Done
/* GPP_F8 - GPIO */
PAD_NC(GPP_F8, NONE),
/* GPP_F9 - GPIO */
PAD_NC(GPP_F9, NONE),
/* GPP_F10 - GPIO */
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
/* GPP_F11 - GPIO */
PAD_NC(GPP_F11, NONE),
/* GPP_F12 - GPIO */
PAD_NC(GPP_F12, NONE),
/* GPP_F13 - GPIO */
PAD_NC(GPP_F13, NONE),
/* GPP_F14 - GPIO */
PAD_NC(GPP_F14, NONE),
/* GPP_F15 - GPIO */
PAD_NC(GPP_F15, NONE),
/* GPP_F16 - GPIO */
PAD_NC(GPP_F16, NONE),
/* GPP_F17 - GPIO */
PAD_NC(GPP_F17, NONE),
/* GPP_F18 - GPIO */
PAD_NC(GPP_F18, NONE),
/* GPP_F19 - GPIO */
PAD_NC(GPP_F19, NONE),
/* GPP_F20 - GPIO */
PAD_NC(GPP_F20, NONE),
/* GPP_F21 - GPIO */
PAD_NC(GPP_F21, NONE),
/* GPP_F22 - GPIO */
PAD_NC(GPP_F22, NONE),
/* GPP_F23 - A4WP_PRESENT */
PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
nc, 20 up
Done
/* GPP_H1 - CNV_RF_RESET# */
PAD_CFG_NF(GPP_H1, UP_20K, D
wired statically -> nc, none
Done
/* GPP_H2 - MODEM_CLKREQ */
PAD_CFG_NF(GPP_H2, UP_20K, DEEP, N
same as h0, nc, none
Done
* GPP_H4 - GPIO */
PAD_NC(GPP_H4, NONE),
/* GPP_H5 - GPIO */
PAD_NC(GPP_H5, NONE),
nc, up 20
Done
GPP_H10 - I2C5_SDA */
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
/* GPP_H11 - I2C5_SCL */
PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
nc, none
Done
Patch Set #3, Line 387: PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
nc, 20 up
Done
/* GPP_H19 - GPIO */
PAD_CFG_GPO(GPP_H19, 1, PLTRST),
/* GPP_H20 - GPIO */
PAD_NC(GPP_H20, NONE),
nc, 20 up
Done
Patch Set #3, Line 399: PAD_CFG_GPO(GPP_H22, 1, PLTRST),
nc 20 up
Done
Patch Set #3, Line 402: PAD_CFG_GPO(GPP_H23, 0, DEEP),
nc, none
Done
Patch Set #3, Line 413: PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1),
nc, none
Done
Patch Set #3, Line 425: PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
nc, 20 up
Done
Patch Set #3, Line 428: PAD_CFG_GPO(GPD7, 0, DEEP),
nc, none
Done
Patch Set #3, Line 434: PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
nc, 20 up
Done
Patch Set #3, Line 437: PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
nc 20 up
Done
Patch Set #3, Line 440: PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
nc 20 up
Done
Patch Set #3, Line 451: PAD_CFG_GPO(GPP_C2, 1, DEEP),
nc, none
Done
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* GPP_C4 - SML0DATA */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
nc, none
Done
Patch Set #3, Line 460: PAD_CFG_GPO(GPP_C5, 1, PLTRST),
nc, up 20
Done
PAD_CFG_GPO(GPP_C8, 1, PLTRST),
/* GPP_C9 - GPIO */
PAD_CFG_GPO(GPP_C9, 1, PLTRST),
could be configured as uart on R26 (TX), R206 (RX) - or NC, none
Done
/* GPP_C10 - GPIO */
PAD_CFG_GPO(GPP_C10, 0, PLTRST),
/* GPP_C11 - GPIO */
PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE),
/* GPP_C12 - UART1_RXD */
PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
/* GPP_C13 - UART1_TXD */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
/* GPP_C14 - UART1_RTS# */
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
/* GPP_C15 - UART1_CTS# */
PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1),
all nc, up 20
Done
AD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
/* GPP_C17 - I2C0_SCL */
PAD_CFG_NF(GPP_C17, NONE, PLTRST,
nc, none
Done
P_C18 - I2C1_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* GPP_C19 - I2C1_SCL */
PAD_CFG_NF(GPP_C19, NONE,
nc, up 20
Done
20 - GPIO */
PAD_NC(GPP_C20, NONE),
/* GPP_C21 - GPIO */
PAD_NC(GPP_C21, NONE),
could be configured as uart with R653 (TX), R654 (RX) - or NC, none
Done
USB3_P1_PWREN
Done; see CB:47220
PP_C23 - GPIO */
PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NO
nc, 20 up
Done
PP_E0 - GPIO */
PAD_NC(GPP_E0, NONE),
/* GPP_E1 - GPIO */
PAD_NC(GPP_E1, NONE),
nc, 20 up
Done
Patch Set #3, Line 528: PAD_CFG_GPI_SMI(GPP_E3, NONE,
nc,up 20
Done
Patch Set #3, Line 531: PAD_CFG_GPO(GPP_E4, 1, PLTRST),
nf1 / devlsp0
Done; see CB:47220
GPP_E5 - GPIO */
PAD_NC(GPP_E5, NONE),
/* GPP_E6 - GPIO */
PAD_NC(GPP_E6, NONE),
nc, up 20
Done
Patch Set #3, Line 540: G_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI),
nc, none
Done
PP_E9 - RESERVED */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5),
/* GPP_E10 - RESERVED */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5),
lolwat. NF5. […]
Done; see CB:47220, CB:47222
Patch Set #3, Line 564: _GPO(GPP_E15, 1,
nc, none
Done
Patch Set #3, Line 570: PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
nc, none
Done
/* GPP_E20 - DPPC_CTRLCLK */
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* GPP_E21 - DPPC_CTRLDATA */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
nc, none
Done
Patch Set #3, Line 585: PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1),
nc, up 20
Done
Patch Set #3, Line 588: PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1),
nc, none
Done
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