[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs

[EricR Lai (Code Review)]

Attention is currently required from: Tim Crawford, Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60182 )

Change subject: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
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Patch Set 5:

(1 comment)

Patchset:

PS5: 
I see, maybe we can create another .c file to let romstage/ramstage call the same one.