[coreboot-gerrit] Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Correct xHCI sleep workaround

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49130 )

Change subject: [UNTESTED] sb/intel/bd82x6x: Correct xHCI sleep workaround
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Patch Set 2: Code-Review+1

(1 comment)

looks correct from your description, i couldn't find the panther point pch bios spec

https://review.coreboot.org/c/coreboot/+/49130/2/src/southbridge/intel/bd82x... 
File src/southbridge/intel/bd82x6x/smihandler.c:

https://review.coreboot.org/c/coreboot/+/49130/2/src/southbridge/intel/bd82x... 
PS2, Line 153: PCI_BASE_ADDRESS_0 + 4
nit: PCI_BASE_ADDRESS_1 or I wonder if a new macro, PCI_BASE_ADDRESS_0_UPPER or similar would be more helpful for 64-bit BARs?