Patch Set 1:

Can you describe at a high level how the boot flow for this platform will look like? What are your reasons for running the romstage from DRAM rather than skipping it entirely?

Also, in the other patch you mention that bootblock and verstage may run on the PSP... how is it going to transition from there? Would it maybe make sense to run the romstage on the PSP instead?

It was going to take significant additional changes to coreboot to begin x86 execution with ramstage (e.g. cbmem is assumed already to be online). As a result, we chose to do a small romstage, at least for now.

Here's the current general flow - I'm working on a design doc and will publish something both internally and at coreboot.org about the boot flow.

- Power On - PSP starts from On-Chip firmware
- PSP loads minimal off-chip firmware from the SPI ROM.
- PSP tries to load coreboot verstage from SPI.
   - If verstage is available, it does its verification and passes the AMD firmware directory table for the chosen FMAP region back to the PSP to load everything else.
   - If verstage is not available, the PSP continues from the original AMD firmware directory table.
- PSP loads the ABL (AGESA Boot Loader) code and runs that.
- The ABL loads the APCB (AGESA PSP Customization Block), a structure containing the setup for AGESA running in the PSP.  This contains a number of configuration options as well as the information how to get the SPDs.
- ABL initializes memory.  I discussed with AMD whether we could continue to let coreboot do the memory initialization instead of the PSP, but the ability to do Cache-as-RAM has been removed, so while it might be possible, it would have to be all written in ASM.
- PSP looks up the code destinations in the AMD firmware directory table then decompresses and copies the rest of the FMAP region into memory.  It fixes up the x86 CS descriptor to appear to BIOS as any x86 does coming out of reset, except CS's base points to DRAM and not flash.  The base is romstage_base + romstage_size - 64KB and IP=0xfff0.
- PSP jumps to the x86 reset vector, in this case coreboot's romstage.

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