sb/intel/common: Create a common PCH finalise implementation

The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.

Lynx Point now benefits from being able to write-protect the flash chip.

For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.

Also, remove the post code `POST_OS_BOOT`, as it's not guaranteed to be
the last post code before the OS boots.

Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.

Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.

Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
---
M src/mainboard/lenovo/x201/smihandler.c
M src/mainboard/packardbell/ms2290/smihandler.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/Makefile.inc
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
R src/southbridge/intel/common/finalize.c
A src/southbridge/intel/common/finalize.h
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/Makefile.inc
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
D src/southbridge/intel/lynxpoint/finalize.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/smihandler.c
20 files changed, 112 insertions(+), 142 deletions(-)