1 comment:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #1, Line 72: register "PcieClkSrcUsage[0]" = "0x40"
As far as I understand it, this configures PCH CLKSRC 0 to be used for CPU PCIe RP 1.
you are right, this is all due to wrong naming in FSP, ideally this is CPU RP 1 getting PEG clk 0
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