Patch Set 5:
General boot-flow document:
https://doc.coreboot.org/soc/amd/family17h.htmlThanks for providing that doc, it makes many things clearer. However, I still don't really follow why running a separate romstage (and apparently also postcar?) binary in DRAM is the best/easiest way to model this boot flow.
It's the way we have working currently. Ultimately we may try to go back and move everything into ramstage, but that presents additional problems. We realize that there are issues with our current approach, but at least for now we still need romstage, as it's required to load AGESA.
Besides, if if we do everything in ramstage and Ron removes ramstage for linuxboot, what's left?
...
(I'm also curious about how verstage can interact with the rest of the PSP boot flow. Can an RW update be used to update the ABL code or the APCB data? That's not really clear from the doc.)
verstage will be called from the PSP, run, and pass back the pointer to the correct directory (RW-A, RW-B or RO). The PSP will load all the rest of the configuration, including the APCB from that directory.
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