Michał Żygowski has uploaded this change for review.
amdblocks/pci: add common implementation of MMCONF enabling
Add common function to enable PCI MMCONF base address. Use the common
function in stoneyridge bootblock. Enable the common implementation for
other AMD southbridges for use in C bootblock.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037
---
A src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h
M src/soc/amd/common/block/pci/Kconfig
M src/soc/amd/common/block/pci/Makefile.inc
A src/soc/amd/common/block/pci/amd_pci_mmconf.c
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/southbridge/amd/agesa/hudson/Kconfig
M src/southbridge/amd/cimx/sb800/Kconfig
M src/southbridge/amd/pi/hudson/Kconfig
8 files changed, 62 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37552/1
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h
new file mode 100644
index 0000000..4b65ad0
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_PCI_MMCONF_H__
+#define __AMDBLOCKS_PCI_MMCONF_H__
+
+void enable_pci_mmconf(void);
+
+#endif
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig
index 74ea697..d4efe00 100644
--- a/src/soc/amd/common/block/pci/Kconfig
+++ b/src/soc/amd/common/block/pci/Kconfig
@@ -4,3 +4,10 @@
help
This option builds functions used to program PCI interrupt
routing, both PIC and APIC modes.
+
+config SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ bool
+ default n
+ help
+ This option builds function used to program PCI MMIO configuration
+ base address.
diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc
index fc40c9d..b20da88 100644
--- a/src/soc/amd/common/block/pci/Makefile.inc
+++ b/src/soc/amd/common/block/pci/Makefile.inc
@@ -1,5 +1,6 @@
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
-ramstage-y += amd_pci_util.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c
-endif
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF) += amd_pci_mmconf.c
diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
new file mode 100644
index 0000000..1aed51b
--- /dev/null
+++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <amdblocks/amd_pci_mmconf.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+void enable_pci_mmconf(void)
+{
+ msr_t mmconf;
+
+ mmconf.hi = 0;
+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
+ | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
+ wrmsr(MMIO_CONF_BASE, mmconf);
+}
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index d92535a..9920aff 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -24,6 +24,7 @@
#include <bootblock_common.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
+#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
@@ -42,15 +43,9 @@
/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
static void amd_initmmio(void)
{
- msr_t mmconf;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int mtrr;
- mmconf.hi = 0;
- mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
- | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
- wrmsr(MMIO_CONF_BASE, mmconf);
-
/*
* todo: AGESA currently writes variable MTRRs. Once that is
* corrected, un-hardcode this MTRR.
@@ -75,6 +70,7 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ enable_pci_mmconf();
amd_initmmio();
/*
* Call lib/bootblock.c main with BSP, shortcut for APs
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 93db1a9..4fe770d 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -30,6 +30,7 @@
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 0b790b0..23a6c4a 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -24,6 +24,7 @@
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 01f3937..8a52b64 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -33,6 +33,7 @@
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
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