Patch Set 3:

gentle ping

I have no idea how the defines could be useful for
mainboard code; and it seems there is no push of
the latter to look at how they are used?

Generally I wonder, why the mainboard code would
have to poke registers. We have APIs for device
access (maybe something is missing for APL, though).

In my mainboard KConfig I have this now:

config BOARD_SPECIFIC_OPTIONS
	def_bool y
	select SOC_INTEL_APOLLOLAKE
	select SOC_INTEL_COMMON_BLOCK_SMBUS <---
	..

As it was not accepted to select SOC_INTEL_COMMON_BLOCK_SMBUS in generic APL code I need to do it in my mainboard code cause of GPIO settings. And this ends in this compile error.

    CC         ramstage/soc/intel/common/block/smm/smm.o
    CC         ramstage/soc/intel/common/block/smbus/smbus.o
src/soc/intel/common/block/smbus/smbus.c: In function 'pch_smbus_init':
src/soc/intel/common/block/smbus/smbus.c:65:8: error: 'SMBUS_SLAVE_ADDR' undeclared (first use in this function); did you mean 'SMBUS_ERROR'?
   outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
        ^~~~~~~~~~~~~~~~
        SMBUS_ERROR
src/soc/intel/common/block/smbus/smbus.c:65:8: note: each undeclared identifier is reported only once for each function it appears in
src/soc/intel/common/block/smbus/smbus.c:65:38: error: 'SMB_RCV_SLVA' undeclared (first use in this function)
   outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
                                      ^~~~~~~~~~~~
make: *** [Makefile:356: build/ramstage/soc/intel/common/block/smbus/smbus.o] Fehler 1

Do may ask why I need this at all - I need to readout the params used to init the memory from an eeprom connected via smbus that does _NOT_ contain SPD.

void mainboard_memory_init_params(FSPM_UPD *mupd)
{
	uint8_t buf[0x100] = { 0 };
	int i;

	/* setup early gpio before memory */
	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

	for (i = 0; i < ARRAY_SIZE(buf); i++)
		buf[i] = smbus_read_byte(0, 0x50, i);

	struct memory_config *m = (struct memory_config *) buf;
	mupd->FspmConfig.Package = m->package;
	mupd->FspmConfig.Profile = m->profile;
	mupd->FspmConfig.MemoryDown = m->memory_down;
	mupd->FspmConfig.DDR3LPageSize = m->DDR3LPageSize;
	mupd->FspmConfig.DDR3LASR = m->DDR3LASR;
	mupd->FspmConfig.ScramblerSupport = m->scrambler_support;
	mupd->FspmConfig.InterleavedMode = m->interleaved_mode;
	mupd->FspmConfig.ChannelHashMask = m->channel_hash_mask;
	mupd->FspmConfig.SliceHashMask = m->slice_hash_mask;
	mupd->FspmConfig.ChannelsSlicesEnable = m->channels_slices_enable;
	mupd->FspmConfig.MinRefRate2xEnable = m->min_ref_rate_2x_enable;
	mupd->FspmConfig.DualRankSupportEnable = m->dual_rank_support_enable;
	mupd->FspmConfig.RmtMode = m->rmt_mode;
	mupd->FspmConfig.MemorySizeLimit = m->memory_size_limit;
	mupd->FspmConfig.LowMemoryMaxValue = m->low_memory_max_value;
	mupd->FspmConfig.HighMemoryMaxValue = m->high_memory_max_value;
	mupd->FspmConfig.DisableFastBoot = m->disable_fast_boot;
	mupd->FspmConfig.DIMM0SPDAddress = m->spd_address_0;
	mupd->FspmConfig.DIMM1SPDAddress = m->spd_address_1;
	mupd->FspmConfig.Ch0_RankEnable = m->ch0_rank_enable;
	mupd->FspmConfig.Ch0_DeviceWidth = m->ch0_device_width;
	mupd->FspmConfig.Ch0_DramDensity = m->ch0_dram_density;
	mupd->FspmConfig.Ch0_Option = m->ch0_option;
	mupd->FspmConfig.Ch0_OdtConfig = m->ch0_odt_config;
	mupd->FspmConfig.Ch0_TristateClk1 = m->ch0_tristateClk1;
	mupd->FspmConfig.Ch0_Mode2N = m->ch0_Mode2N;
	mupd->FspmConfig.Ch0_OdtLevels = m->ch0_OdtLevels;
	mupd->FspmConfig.Ch1_RankEnable = m->ch1_rank_enable;
	mupd->FspmConfig.Ch1_DeviceWidth = m->ch1_device_width;
	mupd->FspmConfig.Ch1_DramDensity = m->ch1_dram_density;
	mupd->FspmConfig.Ch1_Option = m->ch1_option;
	mupd->FspmConfig.Ch1_OdtConfig = m->ch1_OdtLevels;
	mupd->FspmConfig.Ch1_TristateClk1 = m->ch1_tristateClk1;
	mupd->FspmConfig.Ch1_Mode2N = m->ch1_Mode2N;
	mupd->FspmConfig.Ch1_OdtLevels = m->ch1_OdtLevels;
	mupd->FspmConfig.Ch2_RankEnable = m->ch2_rank_enable;
	mupd->FspmConfig.Ch2_DeviceWidth = m->ch2_device_width;
	mupd->FspmConfig.Ch2_DramDensity = m->ch2_dram_density;
	mupd->FspmConfig.Ch2_Option = m->ch2_option;
	mupd->FspmConfig.Ch2_OdtConfig = m->ch2_odt_config;
	mupd->FspmConfig.Ch2_TristateClk1 = m->ch2_tristateClk1;
	mupd->FspmConfig.Ch2_Mode2N = m->ch2_Mode2N;
	mupd->FspmConfig.Ch2_OdtLevels = m->ch2_OdtLevels;
	mupd->FspmConfig.Ch3_RankEnable = m->ch3_rank_enable;
	mupd->FspmConfig.Ch3_DeviceWidth = m->ch3_device_width;
	mupd->FspmConfig.Ch3_DramDensity = m->ch3_dram_density;
	mupd->FspmConfig.Ch3_Option = m->ch3_option;
	mupd->FspmConfig.Ch3_OdtConfig = m->ch3_odt_config;
	mupd->FspmConfig.Ch3_TristateClk1 = m->ch3_tristateClk1;
	mupd->FspmConfig.Ch3_Mode2N = m->ch3_Mode2N;
	mupd->FspmConfig.Ch3_OdtLevels = m->ch3_OdtLevels;
	mupd->FspmConfig.RmtCheckRun = m->rmt_check_run;
	mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = m->rmt_margin_chk_scale_hi_threshold;

	memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, m->ch0_bitSwizzling, sizeof(m->ch0_bitSwizzling));
	memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, m->ch1_bitSwizzling, sizeof(m->ch1_bitSwizzling));
	memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, m->ch2_bitSwizzling, sizeof(m->ch2_bitSwizzling));
	memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, m->ch3_bitSwizzling, sizeof(m->ch3_bitSwizzling));
}

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