Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14966
-gerrit
commit d552127357e3f1ebaa443c1fc98b7406b5ea030c Author: Hannah Williams hannah.williams@intel.com Date: Wed May 25 11:12:43 2016 -0700
soc/apollolake: remove _RMV and _DSW methods from xhci.asl
Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/soc/intel/apollolake/acpi/xhci.asl | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index fc67074..c07c707 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -1,4 +1,5 @@ -/* This file is part of the coreboot project. +/* + * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corporation. * @@ -13,29 +14,18 @@ */
/* XHCI Controller 0:15.0 */ -Device(XHC1) { - Name(_ADR, 0x00150000) // Device 21, Function 0 +Device (XHC1) { + Name (_ADR, 0x00150000) /* Device 21, Function 0 */
Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */
- // Declare XHCI GPE status and enable bits are bit 13 + /* Declare XHCI GPE status and enable bits are bit 13 */ Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 })
- Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake - { - Return (Zero) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Method(_STA, 0) + Method (_STA, 0) { Return (0xF) } - }