Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Andrey Petrov, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50608 )
Change subject: vc/google/chromeos: Always CHROMEOS_RAMOOPS_DYNAMIC ......................................................................
vc/google/chromeos: Always CHROMEOS_RAMOOPS_DYNAMIC
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START.
Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/ramoops.c 17 files changed, 3 insertions(+), 111 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/50608/1
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5b92842..e3f9aec 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -25,9 +25,6 @@ binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index e06bdac..215560f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -32,9 +32,6 @@ binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 410048f..6404397 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -313,7 +313,6 @@ choose to generate _PSD object to allow cores to transition together.
config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1c69454..916e5f3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -213,9 +213,6 @@ hex default 0x7fff
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 62049b5..9fe2c29 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -114,9 +114,6 @@ int default 4
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 55615ac..6d91d58 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,9 +37,6 @@ select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4260b5d..fcf07fa 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -52,9 +52,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages.
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf84f7a..7528c09 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -73,9 +73,6 @@ binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 49ec1b1..dd7d699 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -260,9 +260,6 @@ hex default 0xc35
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 25804d7..3b17a0ed 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -171,9 +171,6 @@ hex default 0xc35
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 501e6c3..f28209f 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -164,9 +164,6 @@ hex default 0xc35
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 08bd4be..72912f7 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -172,9 +172,6 @@ hex default 0xc35
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7401d5e..a7e25b1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -92,9 +92,6 @@ int default 10
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3e080cc..c6bb167 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -191,9 +191,6 @@ hex default 0x7fff
-config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. config TPM_CR50 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index d5254ac..e81f31d 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -29,21 +29,6 @@ bool "Reserve space for Chrome OS ramoops" default y
-config CHROMEOS_RAMOOPS_DYNAMIC - bool "Allocate RAM oops buffer in cbmem" - default n - depends on CHROMEOS_RAMOOPS && HAVE_ACPI_TABLES - -config CHROMEOS_RAMOOPS_NON_ACPI - bool "Allocate RAM oops buffer in cbmem passed through cb tables to payload" - default y if !HAVE_ACPI_TABLES - depends on CHROMEOS_RAMOOPS && !HAVE_ACPI_TABLES - -config CHROMEOS_RAMOOPS_RAM_START - hex "Physical address of preserved RAM" - default 0x00f00000 - depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC - config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" default 0x00100000 diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index d023075..35e2dde 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -27,10 +27,7 @@ */ void mainboard_prepare_cr50_reset(void);
-struct romstage_handoff; - #include "gnvs.h" -struct device;
#if CONFIG(CHROMEOS_RAMOOPS) void chromeos_ram_oops_init(chromeos_acpi_t *chromeos); @@ -38,8 +35,6 @@ static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} #endif /* CONFIG_CHROMEOS_RAMOOPS */
-void chromeos_reserve_ram_oops(struct device *dev, int idx); - void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int);
@@ -66,6 +61,7 @@ */ void mainboard_chromeos_acpi_generate(void); #if CONFIG(CHROMEOS) +struct device; void chromeos_dsdt_generator(const struct device *dev); #else #define chromeos_dsdt_generator NULL diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 119912b..ae72133 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -24,66 +24,17 @@ chromeos->ramoops_len = size; }
-static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) +void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) { const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; void *ram_oops;
- if (!CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)) - return; - ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size);
set_ramoops(chromeos, ram_oops, size); }
-#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC) -static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {} -#else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ - -static const unsigned long ramoops_base = CONFIG_CHROMEOS_RAMOOPS_RAM_START; -static const unsigned long ramoops_size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; - -/* - * Save pointer to chromeos structure in memory. This is needed because the - * memory reservation is not done when chromeos_init() is called. However, - * the pointer to the chromeos_acpi_t structure is needed to update the - * fields with the rserved base and size. - */ -static chromeos_acpi_t *g_chromeos; - -static void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) -{ - g_chromeos = chromeos; -} - -static void update_gnvs(void *arg) -{ - chromeos_acpi_t **chromeos = arg; - - set_ramoops(*chromeos, (void *)ramoops_base, ramoops_size); -} - -static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &g_chromeos); - -void chromeos_reserve_ram_oops(struct device *dev, int idx) -{ - const unsigned long base = ramoops_base >> 10; - const unsigned long size = ramoops_size >> 10; - - reserved_ram_resource(dev, idx, base, size); - - boot_state_sched_on_exit(&bscb_ramoops, BS_WRITE_TABLES); -} -#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ - -void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) -{ - set_global_chromeos_pointer(chromeos); - reserve_ram_oops_dynamic(chromeos); -} - -#elif CONFIG(CHROMEOS_RAMOOPS_NON_ACPI) +#else
static void ramoops_alloc(void *arg) {