Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12322
-gerrit
commit 5d3fcb9dc09e170b05f59c8fd86f8688d095a482 Author: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Date: Mon Oct 19 14:45:23 2015 +0530
intel/skylake: Add Fan control support
This patch adds the ASL file for Fan as cooling device /participant for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. With active cooling policy (_ART), we can control the fan on/off and speed.
BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface.
Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4 Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf Original-Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/307027 Original-Commit-Ready: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Original-Tested-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Original-Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/acpi/dptf/dptf.asl | 18 ++++++++ src/soc/intel/skylake/acpi/dptf/fan.asl | 72 ++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+)
diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 4f1c564..61f982c 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -29,6 +29,11 @@ Device (DPTF)
/* DPPM Cooling Policy */ ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* DPPM Active Policy */ + ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"), +#endif })
Method (_STA) @@ -71,6 +76,14 @@ Device (DPTF) Return (_SB.DTRT) }
+#ifdef DPTF_ENABLE_FAN_CONTROL + /* _ART : Active Cooling Relationship Table */ + Method (_ART) + { + Return (_SB.DART) + } +#endif + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ @@ -90,6 +103,11 @@ Device (DPTF) #include "charger.asl" #endif
+#ifdef DPTF_ENABLE_FAN_CONTROL + /* Include Fan Participant */ + #include "fan.asl" +#endif + }
Scope (_SB.PCI0) diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl new file mode 100644 index 0000000..0501385 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device (TFN1) +{ + Name (_HID, "INT3404") + Name (_UID, 0) + Name (_STR, Unicode("Fan Control")) + + /* _FIF: Fan Information */ + Name (_FIF, Package () + { + 0, // Revision + 1, // Fine Grained Control + 2, // Step Size + 0 // No Low Speed Notification + }) + + /* Return Fan Performance States defined by mainboard */ + Method (_FPS) + { + Return (_SB.DFPS) + } + + Name (TFST, Package () + { + 0, // Revision + 0x00, // Control + 0x00 // Speed + }) + + /* _FST: Fan current Status */ + Method (_FST, 0, Serialized,,PkgObj) + { + /* Fill in TFST with current control. */ + Store (_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + Return (TFST) + } + + /* _FSL: Fan Speed Level */ + Method (_FSL, 1, Serialized) + { + Store (Arg0, _SB.PCI0.LPCB.EC0.FAND) + Notify (DPTF, 0x83) // Re evaluate _ART + } + + Method (_STA) + { + If (LEqual (\DPTE, One)) + { + Return (0xF) + } Else { + Return (0x0) + } + } +}