10 comments:
File src/soc/mediatek/mt8192/include/soc/pmif_spi.h:
Patch Set #1, Line 89: SPI_CLK = 0x1,
code indent should use tabs where possible
please fix the tab below.
File src/soc/mediatek/mt8192/include/soc/pmif_spmi.h:
replace 89 by the real GPIO name.
Patch Set #1, Line 27: SPMI_SCL_GPIO
enum
open brace '{' following enum go on the same line
enum {
File src/soc/mediatek/mt8192/pmif.c:
Patch Set #1, Line 115: ((read32(&arb->mtk_pmif->init_done) & 0x1))
if (read32() & 0x1)
int ret = 1;
ret = pmif_clk_init();
if (ret)
goto FAIL;
ret = pmif_spmi_init(&pmif_spmi_arb[SPMI_MASTER_0]);
if (ret)
goto FAIL;
ret = pmif_spi_init(&pmif_spi_arb[0]);
if (ret)
goto FAIL;
return 0;
FAIL:
/* assert(0); */
return ret;
int ret;
ret = pmif_clk_init();
if (!ret)
ret = pmif_spmi_init(&pmif_spmi_arb[SPMI_MASTER_0]);
if (!ret)
ret = pmif_spi_init(&pmif_spi_arb[0]);
return ret;
File src/soc/mediatek/mt8192/pmif_clk.c:
#define FREQ_260MHZ 260
/* calibation miss rate, unit: 0.1% */
#define CAL_MIS_RATE 40
/*
* FREQ METER ID
* Ask clkmgr owner to find this information
* at clock table[fmeter].
*/
#define FREQ_METER_ABIST_AD_OSC_CK 37
#define CAL_MAX_VAL 0x7f
use enum
id
) | (
Patch Set #1, Line 66: write32
consider SET32_BITFIELD?
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