Patrick Georgi submitted this change.

View Change

sb/intel/lynxpoint/lpc.c: Relocate lock bit write

This lock bit can be set later, and should also be set for LynxPoint-H.
This eases merging with Broadwell, which already sets this lock bit
after `spi_finalize_ops()` in a dedicated finalisation function.

Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set.

Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/southbridge/intel/lynxpoint/lpc.c
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index cf80e64..55157a8 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -485,9 +485,6 @@
 	if (RCBA32(FD) & PCH_DISABLE_ADSPD)
 		RCBA32_OR(0x2b1c, (1 << 29));
 
-	/* Lock */
-	RCBA32_OR(0x3a6c, 0x00000001);
-
 	/* Set RCBA 0x33D4 after other setup */
 	RCBA32_OR(0x33d4, 0x2fff2fb1);
 
@@ -809,6 +806,9 @@
 {
 	spi_finalize_ops();
 
+	/* Lock */
+	RCBA32_OR(0x3a6c, 0x00000001);
+
 	if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
 		apm_control(APM_CNT_FINALIZE);
 }

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