6 comments:
Patch Set #2, Line 9: ByteLane is incorrectly used unitialized from prior for statement.
Might be bad coding style, not incorrect per-se. There is A potential out-of-bound read of RxOrig[MaxByteLanes].
Patch Set #2, Line 11: PassTestRxEnDly at that index, so appears safe to delete.
Rephrase perhaps: PassTestRxEnDly[MaxByteLanes] never appears as rvalue, all for loops have ByteLane < MaxByteLanes exit condition.
Patch Set #2, Line 14: 'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'.
I did not understand this comment.
File src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c:
Patch Set #2, Line 329: if ((RxEn >= NBPtr->MinRxEnSeedGross) && (RxEn <= NBPtr->MaxRxEnSeedTotal)) {
For coverity scan, this might evaluate as a static true statement.
Patch Set #2, Line 337: OutOfRange[ByteLane] = TRUE;
... so this path of not setting PassTestRxEndDly might not ever be reached.
Patch Set #2, Line 359: MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);
PassTestRxEnDly could still be unset here?
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