Patch Set 1: Code-Review-1

Dug a little into the chipset support for historical Intel
in the tree: Older ICHs implement the bit r/w but mention
to ignore it anyway, because everything goes to PCI. So that
should be fine.

440BX doesn't seem to know it, though :-/ So this can't go
in as is. I'm open for suggestions. What should we do if
16-bit decode isn't possible? Restrict all i/o to 10 bits?
That could brick... Hmmmm, just warn about it? Instead of
skipping the device?

I really don't like to reserve the VGA resources 64 times,
could do that, though.

The code in device.c seems to attempt to avoid VGA IO and "legacy" PCI IO windows when allocating (dynamic) resources. I am not convinced that code always works, and those windows would appear to be unnecessary for platforms where we can have programming of CTL_VGA=1, CTL_VGA16=1 and CTL_(NO)_ISA=0 for PCI_BRIDGE_CONTROL.

I think we could first throw errors if assigned resources overlap some of those aliased (and enabled) IO address ranges. Should be easy to (manually) adjust the conflicting static resources when they appear.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Gerrit-Change-Number: 35516
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <>
Gerrit-Reviewer: Kyösti Mälkki <>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <>
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