Arthur Heymans uploaded patch set #2 to this change.

View Change

nb/intel/x4x: Switch to POSTCAR_STAGE

Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
D src/cpu/intel/car/cache_as_ram_ht.inc
M src/cpu/intel/socket_LGA775/Makefile.inc
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/ram_calc.c
5 files changed, 12 insertions(+), 477 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/26787/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267
Gerrit-Change-Number: 26787
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>