Attention is currently required from: Arthur Heymans, Maciej Pijanowski, Martin L Roth, Michał Żygowski, ron minnich.
Sergii Dmytruk uploaded patch set #28 to this change.
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.
If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
---
M src/arch/ppc64/Makefile.mk
M src/arch/ppc64/bootblock_crt0.S
M src/mainboard/emulation/qemu-power8/memlayout.ld
M src/mainboard/emulation/qemu-power9/memlayout.ld
M src/mainboard/raptor-cs/talos-2/Kconfig
A src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd
A src/mainboard/raptor-cs/talos-2/board.fmd
M src/mainboard/raptor-cs/talos-2/memlayout.ld
M src/soc/ibm/power9/Makefile.inc
9 files changed, 344 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/67067/28
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