Piotr Kleinschmidt has uploaded this change for review.

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mb/pcengines/apu2: use older AGESA with different headers

PC Engines apu2 platforms use AGESA 1.0.0.4 which uses
different AGESA.h header than newer AGESA versions.

Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
---
M src/mainboard/pcengines/apu2/Kconfig
M src/vendorcode/amd/pi/00730F01/AGESA.h
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35906/1

diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 6c3958b..5a61ed1 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -114,4 +114,8 @@
 	int
 	default 128
 
+config AGESA_USE_OLD_HEADER
+	bool
+	default y
+
 endif # BOARD_PCENGINES_APU2
diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h
index c25b631..6053f3c 100644
--- a/src/vendorcode/amd/pi/00730F01/AGESA.h
+++ b/src/vendorcode/amd/pi/00730F01/AGESA.h
@@ -775,6 +775,7 @@
   DP_VS_0_4V_9_5DB = 0x18                                 ///< 0x18
 } DP_FIXED_VOLT_SWING_TYPE;
 
+#if CONFIG(AGESA_USE_OLD_HEADER)
 /// Alternative DRAM MAC
 typedef enum {
   MAC_UNTESTEDMAC,                               ///< Assign 0 to Untested MAC
@@ -785,6 +786,7 @@
   MAC_300k,                                      ///< Assign 5 to 300k
   MAC_200k,                                      ///< Assign 6 to 200k
 } DRAM_MAXIMUM_ACTIVATE_COUNT;
+#endif
 
 // Macro for statically initializing various structures
 #define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
@@ -1547,7 +1549,9 @@
                                   ///<  667 (MHz)
                                   ///<  800 (MHz)
                                   ///<  and so on...
+#if CONFIG(AGESA_USE_OLD_HEADER)
   OUT UINT8   Mac;                ///< Maximum Activate Count
+#endif
   OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
   OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
   OUT UINT8   Trp;                ///< DCT Trp (busclocks)
@@ -1803,6 +1807,7 @@
                                    ///<
                                    ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
 
+#if CONFIG(AGESA_USE_OLD_HEADER)
   // Dram Mac Default
 
   IN  UINT8 DramMacDefault;  ///< Default Maximum Activate Count
@@ -1818,6 +1823,7 @@
                              ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
                              // Extended temperature range
 
+#endif
   // Online Spare
 
   IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
@@ -2721,8 +2727,10 @@
   IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
   IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
   IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+#if CONFIG(AGESA_USE_OLD_HEADER)
   IN UINT8   CfgMemoryMacDefault;                 ///< Memory DRAM MAC Default
   IN BOOLEAN CfgMemoryExtendedTemperatureRange;   ///< Memory Extended Temperature Range
+#endif
   IN UINT32  CfgPowerDownMode;                    ///< Power Down Mode.
   IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
   IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.

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