Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15248
-gerrit
commit a64b4444a7f53ff94de005affe340dd35c9a4e8b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Jun 17 22:54:22 2016 +0300
intel/sandybridge: Use common ACPI S3 recovery
There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy.
Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/intel/model_206ax/cache_as_ram.inc | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 10 ++-------- src/northbridge/intel/sandybridge/sandybridge.h | 6 ------ 3 files changed, 2 insertions(+), 35 deletions(-)
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a1f5cc9..e31d42a 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -281,27 +281,6 @@ before_romstage: /* Invalidate the cache again. */ invd
- post_code(0x3c) - -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE >> 2, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - post_code(0x3d)
__main: diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 779f29b..a013ec3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -233,15 +233,9 @@ void northbridge_romstage_finalize(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */
- *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } + acpi_prepare_for_resume(); + /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..af5bd48 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -196,12 +196,6 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
-/* Delegation of resume backup memory so we don't have to - * (slowly) handle backing up OS memory in romstage.c - */ -#define CBMEM_BOOT_MODE 0x610 -#define CBMEM_RESUME_BACKUP 0x614 - #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); }