Nico Huber merged this change.
soc/intel/skl/graphics: Implement panel setup
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper
care of this. The sequence is mostly the same as on older platforms,
with a slightly different configuration of the backlight PWM.
We light the panel up with 50% PWM duty cycle. This often results in
an already rather high perceived brightness, but shouldn't be too
blinding.
Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/graphics.c
2 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a537165..9c8e2bf 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -48,6 +48,18 @@
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
+ /* IGD panel configuration */
+ unsigned int gpu_pp_up_delay_ms;
+ unsigned int gpu_pp_down_delay_ms;
+ unsigned int gpu_pp_cycle_delay_ms;
+ unsigned int gpu_pp_backlight_on_delay_ms;
+ unsigned int gpu_pp_backlight_off_delay_ms;
+ unsigned int gpu_pch_backlight_pwm_hz;
+ enum {
+ GPU_BACKLIGHT_POLARITY_HIGH = 0,
+ GPU_BACKLIGHT_POLARITY_LOW,
+ } gpu_pch_backlight_polarity;
+
/*
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index f563c11..7efc65a 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -16,9 +16,11 @@
#include <bootmode.h>
#include <cbmem.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ops.h>
+#include <device/resource.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/libgfxinit.h>
#include <intelblocks/graphics.h>
@@ -32,10 +34,72 @@
return graphics_get_memory_base();
}
+static void graphics_setup_panel(struct device *dev)
+{
+ struct soc_intel_skylake_config *conf = dev->chip_info;
+ struct resource *mmio_res;
+ uint8_t *base;
+ u32 reg32;
+
+ if (!conf)
+ return;
+
+ mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!mmio_res || !mmio_res->base)
+ return;
+ base = (void *)(uintptr_t)mmio_res->base;
+
+ reg32 = conf->gpu_pp_up_delay_ms * 10 << 16;
+ reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10;
+ write32(base + PCH_PP_ON_DELAYS, reg32);
+
+ reg32 = conf->gpu_pp_down_delay_ms * 10 << 16;
+ reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10;
+ write32(base + PCH_PP_OFF_DELAYS, reg32);
+
+ reg32 = read32(base + PCH_PP_DIVISOR);
+ reg32 &= ~0x1f;
+ reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f;
+ write32(base + PCH_PP_DIVISOR, reg32);
+
+ /* So far all devices seem to use the PCH PWM function.
+ The CPU PWM registers are all zero after reset. */
+ if (conf->gpu_pch_backlight_pwm_hz) {
+ /* Reference clock is 24MHz. We can choose either a 16
+ or a 128 step increment. Use 16 if we would have less
+ than 100 steps otherwise. */
+ const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
+ unsigned int pwm_increment, pwm_period;
+ u32 south_chicken1;
+
+ south_chicken1 = read32(base + SOUTH_CHICKEN1);
+ if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+ pwm_increment = 16;
+ south_chicken1 &= ~1;
+ } else {
+ pwm_increment = 128;
+ south_chicken1 |= 1;
+ }
+ write32(base + SOUTH_CHICKEN1, south_chicken1);
+
+ pwm_period = 24 * 1000 * 1000 / pwm_increment
+ / conf->gpu_pch_backlight_pwm_hz;
+ /* Start with a 50% duty cycle. */
+ write32(base + BLC_PWM_PCH_CTL2,
+ pwm_period << 16 | pwm_period / 2);
+
+ write32(base + BLC_PWM_PCH_CTL1,
+ !!conf->gpu_pch_backlight_polarity << 29 |
+ BLM_PCH_PWM_ENABLE);
+ }
+}
+
void graphics_soc_init(struct device *dev)
{
u32 ddi_buf_ctl;
+ graphics_setup_panel(dev);
+
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
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