198 comments:
File src/soc/intel/cannonlake/romstage/romstage.c:
Patch Set #1, Line 273: fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure,
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Patch Set #1, Line 274: new->MrcTimeMeasure);
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Patch Set #1, Line 274: new->MrcTimeMeasure);
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Patch Set #1, Line 302: old->PlatformDebugConsent, new->PlatformDebugConsent);
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Patch Set #1, Line 302: old->PlatformDebugConsent, new->PlatformDebugConsent);
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Patch Set #1, Line 308: old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size);
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Patch Set #1, Line 308: old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size);
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Patch Set #1, Line 310: old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size);
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Patch Set #1, Line 310: old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size);
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Patch Set #1, Line 323: fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit,
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Patch Set #1, Line 324: new->DdrFreqLimit);
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Patch Set #1, Line 324: new->DdrFreqLimit);
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Patch Set #1, Line 325: fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow,
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Patch Set #1, Line 326: new->FreqSaGvLow);
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Patch Set #1, Line 326: new->FreqSaGvLow);
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Patch Set #1, Line 327: #if ! CONFIG(SOC_INTEL_COMETLAKE)
space prohibited after that '!' (ctx:WxW)
Patch Set #1, Line 329: fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid,
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Patch Set #1, Line 330: new->FreqSaGvMid);
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Patch Set #1, Line 330: new->FreqSaGvMid);
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Patch Set #1, Line 332: fsp_display_upd_value("RMT", 1, old->RMT,
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Patch Set #1, Line 333: new->RMT);
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Patch Set #1, Line 333: new->RMT);
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Patch Set #1, Line 334: fsp_display_upd_value("DisableDimmChannel0", 1,
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Patch Set #1, Line 335: old->DisableDimmChannel0, new->DisableDimmChannel0);
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Patch Set #1, Line 335: old->DisableDimmChannel0, new->DisableDimmChannel0);
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Patch Set #1, Line 336: fsp_display_upd_value("DisableDimmChannel1", 1,
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Patch Set #1, Line 337: old->DisableDimmChannel1, new->DisableDimmChannel1);
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Patch Set #1, Line 337: old->DisableDimmChannel1, new->DisableDimmChannel1);
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Patch Set #1, Line 338: fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport,
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Patch Set #1, Line 339: new->ScramblerSupport);
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Patch Set #1, Line 339: new->ScramblerSupport);
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Patch Set #1, Line 340: fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit,
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Patch Set #1, Line 341: new->SkipMpInit);
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Patch Set #1, Line 341: new->SkipMpInit);
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Patch Set #1, Line 343: fsp_display_upd_value("SpdProfileSelected", 1,
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Patch Set #1, Line 344: old->SpdProfileSelected, new->SpdProfileSelected);
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Patch Set #1, Line 344: old->SpdProfileSelected, new->SpdProfileSelected);
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Patch Set #1, Line 345: fsp_display_upd_value("RefClk", 1, old->RefClk,
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Patch Set #1, Line 346: new->RefClk);
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Patch Set #1, Line 346: new->RefClk);
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Patch Set #1, Line 347: fsp_display_upd_value("VddVoltage", 2, old->VddVoltage,
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Patch Set #1, Line 348: new->VddVoltage);
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Patch Set #1, Line 348: new->VddVoltage);
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Patch Set #1, Line 349: fsp_display_upd_value("Ratio", 1, old->Ratio,
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Patch Set #1, Line 350: new->Ratio);
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Patch Set #1, Line 350: new->Ratio);
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Patch Set #1, Line 351: fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode,
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Patch Set #1, Line 352: new->OddRatioMode);
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Patch Set #1, Line 352: new->OddRatioMode);
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Patch Set #1, Line 353: fsp_display_upd_value("tCL", 1, old->tCL,
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Patch Set #1, Line 354: new->tCL);
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Patch Set #1, Line 354: new->tCL);
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Patch Set #1, Line 355: fsp_display_upd_value("tCWL", 1, old->tCWL,
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Patch Set #1, Line 356: new->tCWL);
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Patch Set #1, Line 356: new->tCWL);
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Patch Set #1, Line 357: fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP,
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Patch Set #1, Line 358: new->tRCDtRP);
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Patch Set #1, Line 358: new->tRCDtRP);
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Patch Set #1, Line 359: fsp_display_upd_value("tRRD", 1, old->tRRD,
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Patch Set #1, Line 360: new->tRRD);
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Patch Set #1, Line 360: new->tRRD);
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Patch Set #1, Line 361: fsp_display_upd_value("tFAW", 2, old->tFAW,
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Patch Set #1, Line 362: new->tFAW);
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Patch Set #1, Line 362: new->tFAW);
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Patch Set #1, Line 363: fsp_display_upd_value("tRAS", 2, old->tRAS,
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Patch Set #1, Line 364: new->tRAS);
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Patch Set #1, Line 364: new->tRAS);
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Patch Set #1, Line 365: fsp_display_upd_value("tREFI", 2, old->tREFI,
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Patch Set #1, Line 366: new->tREFI);
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Patch Set #1, Line 366: new->tREFI);
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Patch Set #1, Line 367: fsp_display_upd_value("tRFC", 2, old->tRFC,
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Patch Set #1, Line 368: new->tRFC);
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Patch Set #1, Line 368: new->tRFC);
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Patch Set #1, Line 369: fsp_display_upd_value("tRTP", 1, old->tRTP,
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Patch Set #1, Line 370: new->tRTP);
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Patch Set #1, Line 370: new->tRTP);
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Patch Set #1, Line 371: fsp_display_upd_value("tWR", 1, old->tWR,
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Patch Set #1, Line 372: new->tWR);
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Patch Set #1, Line 372: new->tWR);
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Patch Set #1, Line 373: fsp_display_upd_value("NModeSupport", 1, old->NModeSupport,
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Patch Set #1, Line 374: new->NModeSupport);
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Patch Set #1, Line 374: new->NModeSupport);
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Patch Set #1, Line 375: fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0,
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Patch Set #1, Line 376: new->DllBwEn0);
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Patch Set #1, Line 376: new->DllBwEn0);
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Patch Set #1, Line 377: fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1,
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Patch Set #1, Line 378: new->DllBwEn1);
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Patch Set #1, Line 378: new->DllBwEn1);
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Patch Set #1, Line 379: fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2,
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Patch Set #1, Line 380: new->DllBwEn2);
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Patch Set #1, Line 380: new->DllBwEn2);
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Patch Set #1, Line 381: fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3,
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Patch Set #1, Line 382: new->DllBwEn3);
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Patch Set #1, Line 382: new->DllBwEn3);
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Patch Set #1, Line 383: fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort,
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Patch Set #1, Line 384: new->IsvtIoPort);
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Patch Set #1, Line 384: new->IsvtIoPort);
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Patch Set #1, Line 385: fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode,
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Patch Set #1, Line 386: new->CpuTraceHubMode);
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Patch Set #1, Line 386: new->CpuTraceHubMode);
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Patch Set #1, Line 387: fsp_display_upd_value("CpuTraceHubMemReg0Size", 1,
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Patch Set #1, Line 388: old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size);
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Patch Set #1, Line 388: old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size);
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Patch Set #1, Line 389: fsp_display_upd_value("CpuTraceHubMemReg1Size", 1,
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Patch Set #1, Line 390: old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size);
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Patch Set #1, Line 390: old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size);
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Patch Set #1, Line 391: fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset,
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Patch Set #1, Line 392: new->PeciC10Reset);
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Patch Set #1, Line 392: new->PeciC10Reset);
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Patch Set #1, Line 393: fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset,
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Patch Set #1, Line 394: new->PeciSxReset);
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Patch Set #1, Line 394: new->PeciSxReset);
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Patch Set #1, Line 396: fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable,
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Patch Set #1, Line 397: new->PchHdaEnable);
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Patch Set #1, Line 397: new->PchHdaEnable);
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Patch Set #1, Line 398: fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable,
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Patch Set #1, Line 399: new->PchIshEnable);
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Patch Set #1, Line 399: new->PchIshEnable);
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Patch Set #1, Line 400: fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts,
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Patch Set #1, Line 401: new->HeciTimeouts);
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Patch Set #1, Line 401: new->HeciTimeouts);
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Patch Set #1, Line 403: fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress,
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Patch Set #1, Line 404: new->Heci1BarAddress);
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Patch Set #1, Line 404: new->Heci1BarAddress);
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Patch Set #1, Line 405: fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress,
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Patch Set #1, Line 406: new->Heci2BarAddress);
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Patch Set #1, Line 406: new->Heci2BarAddress);
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Patch Set #1, Line 407: fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress,
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Patch Set #1, Line 408: new->Heci3BarAddress);
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Patch Set #1, Line 408: new->Heci3BarAddress);
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Patch Set #1, Line 409: fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn,
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Patch Set #1, Line 410: new->SgDelayAfterPwrEn);
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Patch Set #1, Line 410: new->SgDelayAfterPwrEn);
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Patch Set #1, Line 411: fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset,
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Patch Set #1, Line 412: new->SgDelayAfterHoldReset);
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Patch Set #1, Line 412: new->SgDelayAfterHoldReset);
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Patch Set #1, Line 413: fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment,
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Patch Set #1, Line 414: new->MmioSizeAdjustment);
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Patch Set #1, Line 414: new->MmioSizeAdjustment);
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Patch Set #1, Line 415: fsp_display_upd_value("DmiGen3ProgramStaticEq", 1,
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Patch Set #1, Line 416: old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq);
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Patch Set #1, Line 416: old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq);
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Patch Set #1, Line 417: fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable,
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Patch Set #1, Line 418: new->Peg0Enable);
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Patch Set #1, Line 418: new->Peg0Enable);
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Patch Set #1, Line 419: fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable,
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Patch Set #1, Line 420: new->Peg1Enable);
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Patch Set #1, Line 420: new->Peg1Enable);
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Patch Set #1, Line 421: fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable,
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Patch Set #1, Line 422: new->Peg2Enable);
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Patch Set #1, Line 422: new->Peg2Enable);
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Patch Set #1, Line 423: fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable,
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Patch Set #1, Line 424: new->Peg3Enable);
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Patch Set #1, Line 424: new->Peg3Enable);
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Patch Set #1, Line 425: fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed,
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Patch Set #1, Line 426: new->Peg0MaxLinkSpeed);
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Patch Set #1, Line 426: new->Peg0MaxLinkSpeed);
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Patch Set #1, Line 427: fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed,
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Patch Set #1, Line 428: new->Peg1MaxLinkSpeed);
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Patch Set #1, Line 428: new->Peg1MaxLinkSpeed);
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Patch Set #1, Line 429: fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed,
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Patch Set #1, Line 430: new->Peg2MaxLinkSpeed);
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Patch Set #1, Line 430: new->Peg2MaxLinkSpeed);
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Patch Set #1, Line 431: fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed,
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Patch Set #1, Line 432: new->Peg3MaxLinkSpeed);
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Patch Set #1, Line 432: new->Peg3MaxLinkSpeed);
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Patch Set #1, Line 433: fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth,
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Patch Set #1, Line 434: new->Peg0MaxLinkWidth);
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Patch Set #1, Line 434: new->Peg0MaxLinkWidth);
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Patch Set #1, Line 435: fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth,
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Patch Set #1, Line 436: new->Peg1MaxLinkWidth);
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Patch Set #1, Line 436: new->Peg1MaxLinkWidth);
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Patch Set #1, Line 437: fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth,
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Patch Set #1, Line 438: new->Peg2MaxLinkWidth);
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Patch Set #1, Line 438: new->Peg2MaxLinkWidth);
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Patch Set #1, Line 439: fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth,
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Patch Set #1, Line 440: new->Peg3MaxLinkWidth);
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Patch Set #1, Line 440: new->Peg3MaxLinkWidth);
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Patch Set #1, Line 441: fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1,
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Patch Set #1, Line 442: old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes);
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Patch Set #1, Line 442: old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes);
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Patch Set #1, Line 443: fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1,
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Patch Set #1, Line 444: old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes);
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Patch Set #1, Line 444: old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes);
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Patch Set #1, Line 445: fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1,
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Patch Set #1, Line 446: old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes);
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Patch Set #1, Line 446: old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes);
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Patch Set #1, Line 447: fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1,
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Patch Set #1, Line 448: old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes);
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Patch Set #1, Line 448: old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes);
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Patch Set #1, Line 449: fsp_display_upd_value("InitPcieAspmAfterOprom", 1,
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Patch Set #1, Line 450: old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom);
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Patch Set #1, Line 450: old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom);
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Patch Set #1, Line 451: fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1,
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Patch Set #1, Line 452: old->PegDisableSpreadSpectrumClocking,
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Patch Set #1, Line 452: old->PegDisableSpreadSpectrumClocking,
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Patch Set #1, Line 453: new->PegDisableSpreadSpectrumClocking);
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Patch Set #1, Line 453: new->PegDisableSpreadSpectrumClocking);
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