Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34872 )
Change subject: google/kukui: Load and run dram init blob ......................................................................
google/kukui: Load and run dram init blob
Load dram.bin and run it for full dram calibration. If any error occurred, try default dram init flow.
BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot
Change-Id: Iad05a77e6353f37cd5ea897203d528762f44176e Signed-off-by: Tristan Shieh tristan.shieh@mediatek.com --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/include/soc/memlayout.ld 3 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34872/1
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..d7621f1 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += dram.bin +dram.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/dram.bin +dram.bin-type := raw +dram.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..8521cf8 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,9 +19,45 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <string.h>
#include "early_init.h"
+#include <cbfs.h> +#include <console/console.h> + +DECLARE_REGION(dram_init_code) + +static int dram_blob_load_and_run(void) +{ + int (*dram_init)(void *); + size_t blob_size, region_size; + + region_size = _edram_init_code - _dram_init_code; + blob_size = cbfs_boot_load_file("dram.bin", _dram_init_code, + region_size, CBFS_TYPE_RAW); + if (blob_size == 0) { + printk(BIOS_ERR, "dram.bin not found\n"); + return -1; + } + + memset(_dram_init_code + blob_size, 0, region_size - blob_size); + + dram_init = (int (*)(void *))_dram_init_code; + + return dram_init(NULL); +} + +static void dram_config(void) +{ + int err = dram_blob_load_and_run(); + if (err == 0) + return; + + printk(BIOS_ERR, "dram_blob error:%d\n", err); + mt_mem_init(get_sdram_config()); +} + void platform_romstage_main(void) { /* This will be done in verstage if CONFIG_VBOOT is enabled. */ @@ -33,6 +69,6 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); - mt_mem_init(get_sdram_config()); + dram_config(); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 7da282e..9a71645 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -24,6 +24,8 @@ */ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4)
SECTIONS { @@ -43,6 +45,7 @@ DECOMPRESSOR(0x00201000, 28K) BOOTBLOCK(0x00208000, 64K) OVERLAP_VERSTAGE_ROMSTAGE(0x00218000, 160K) + DRAM_INIT_CODE(0x00240000, 256K) SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000)