May 2025 - coreboot-gerrit - mail.coreboot.org

[L] Change in coreboot[main]: fit: respect load and entry addresses
by Julius Werner (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Benjamin Doron, Carlos López, Philipp Hug. Julius Werner has posted comments on this change by Carlos López. ( https://review.coreboot.org/c/coreboot/+/87838?usp=email ) Change subject: fit: respect load and entry addresses ...................................................................... Patch Set 3: (2 comments) File src/arch/arm64/fit_payload.c: https://review.coreboot.org/c/coreboot/+/87838/comment/6a37b399_dd72fe6b?us… : PS3, Line 222: if (region->offset == FIT_IMAGE_ADDR_EMPTY) { The whole strict thing is getting pretty complicated. Wouldn't it be easier to just do ``` if (region->offset == FIT_IMAGE_ADDR_EMPTY) { region->offset = addr; ret = bootmem_walk_arg(fit_place_mem, region); } else { ret = bootmem_region_targets_type(region->offset, region->size, BM_MEM_RAM); } ``` ? File src/lib/fit.c: https://review.coreboot.org/c/coreboot/+/87838/comment/15304081_5a14f95c?us… : PS3, Line 133: if (prop->prop.size != 4) { You should rebase onto CB:84796 (which will hopefully soon be ready to go in) which adds all this stuff already. -- To view, visit https://review.coreboot.org/c/coreboot/+/87838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae04d27467a5c55faf146de8e201f53fcbd32aa Gerrit-Change-Number: 87838 Gerrit-PatchSet: 3 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Comment-Date: Thu, 29 May 2025 22:11:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: elog: Handle elog in later boot phase
by Wonkyu Kim (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik. Hello Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87740?usp=email to look at the new patch set (#14). Change subject: elog: Handle elog in later boot phase ...................................................................... elog: Handle elog in later boot phase Use DELAY_SPI_ACCESS to handle elog data later boot phase to avoid flash access delay by other boot controllers. Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU firmwares. Boot-critical firmwares are loaded before CPU reset and non-boot-critical firmwares are loaded during CPU boot. If another controller accesses SPI to load firmwares, reading SPI by CPU is ok, but writing to SPI for saving elog data can take ~32ms sometimes. Saving elog data usually takes less than 1ms. There are three elog handling sequences that need to move together under the Kconfig: - Soc folder - Elog driver folder - ChromeOS folder Before this change, sometimes it delays like below: BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms) After this change, the delay is less than 1 ms: BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms) TEST 1. Enable DEBUG_BOOT_STATE 2. Check time BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)) Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896 Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/drivers/elog/elog.c M src/soc/intel/pantherlake/elog.c M src/vendorcode/google/chromeos/elog.c 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/87740/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/87740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896 Gerrit-Change-Number: 87740 Gerrit-PatchSet: 14 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: security/vboot: Back up CMOS data later boot phase
by Wonkyu Kim (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, Yu-Ping Wu. Hello Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, Subrata Banik, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87738?usp=email to look at the new patch set (#21). Change subject: security/vboot: Back up CMOS data later boot phase ...................................................................... security/vboot: Back up CMOS data later boot phase Introduce DELAY_SPI_ACCESS to save CMOS data in a later boot phase to avoid flash access delay by other boot controllers. Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU firmwares. Boot-critical firmwares are loaded before CPU reset and non-boot-critical firmwares are loaded during CPU boot. If another controller accesses SPI to load firmwares, reading SPI by CPU is ok, but writing to SPI for saving CMOS data can take ~30ms sometimes. Saving CMOS data usually takes less than 1ms. Before this change, sometimes it delays like below: BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (32 ms) After this change, the delay is less than 1 ms: BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (0 ms) TEST 1. Enable DEBUG_BOOT_STATE 2. Check time BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c --- M src/Kconfig M src/security/vboot/vbnv_cmos.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/87738/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/87738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c Gerrit-Change-Number: 87738 Gerrit-PatchSet: 21 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: security/vboot: Back up CMOS data later boot phase
by Wonkyu Kim (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, Yu-Ping Wu. Hello Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, Subrata Banik, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87738?usp=email to look at the new patch set (#20). Change subject: security/vboot: Back up CMOS data later boot phase ...................................................................... security/vboot: Back up CMOS data later boot phase Introduce DELAY_SPI_ACCESS to save CMOS data in a later boot phase to avoid flash access delay by other boot controllers. Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU firmares. Boot-critical firmares are loaded before CPU reset and non-boot-critical firmares are loaded during CPU boot. If another controller accesses SPI to load firmwares, reading SPI by CPU is ok, but writing to SPI for saving CMOS data can take ~30ms sometimes. Saving CMOS data usually takes less than 1ms. Before this change, sometimes it delays like below: BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (32 ms) After this change, the delay is less than 1 ms: BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (0 ms) TEST 1. Enable DEBUG_BOOT_STATE 2. Check time BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c --- M src/Kconfig M src/security/vboot/vbnv_cmos.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/87738/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/87738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c Gerrit-Change-Number: 87738 Gerrit-PatchSet: 20 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: security/vboot: Back up CMOS data later boot phase
by Wonkyu Kim (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, Yu-Ping Wu. Wonkyu Kim has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87738?usp=email ) Change subject: security/vboot: Back up CMOS data later boot phase ...................................................................... Patch Set 19: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/87738/comment/300665b0_665084e8?us… : PS18, Line 1574: simultaneous accesses from other other SPI masters like CSE. > > `Possible repeated word: 'other'` […] Done https://review.coreboot.org/c/coreboot/+/87738/comment/a6344467_23277dbb?us… : PS18, Line 1575: SOCs( > ```SoCs (``` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c Gerrit-Change-Number: 87738 Gerrit-PatchSet: 19 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 May 2025 20:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: security/vboot: Back up CMOS data later boot phase
by Wonkyu Kim (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Wonkyu Kim, Yu-Ping Wu. Hello Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, Subrata Banik, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87738?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/vboot: Back up CMOS data later boot phase ...................................................................... security/vboot: Back up CMOS data later boot phase Introduce DELAY_SPI_ACCESS to save CMOS data later boot phase to avoid flash access delay by other boot controller. Intel has pre-CPU boot controllers(ex. CSE) which load non CPU FWs. Boot critical FWs are loaded before CPU reset and non boot critical boot FWs are loaded during CPU boot. If other controller accesses spi to load FWs, reading spi by CPU is ok but writing SPI time for saving CMOS data takes ~30ms sometimes. Saving CMOS data takes less than 1ms usually. Before this change, sometime it delays like below BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (32 ms) Atfer this change, the delay is less than 1 ms BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:122 (0 ms) TEST 1. enable DEBUG_BOOT_STATE 2. check time BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c --- M src/Kconfig M src/security/vboot/vbnv_cmos.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/87738/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/87738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c Gerrit-Change-Number: 87738 Gerrit-PatchSet: 19 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Update flash layout
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded a new patch set (#3) to the change originally created by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/87860?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Update flash layout ...................................................................... mb/google/fatcat: Update flash layout This patch updates the flash layout for the fatcat variants. The changes are as follows, SI_ALL: 8MB --> 9MB SI_BIOS: 24MB --> 23MB BUG=b:419831198 TEST=Able to build and boot google/fatcat Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/chromeos.fmd 1 file changed, 17 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/87860/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c Gerrit-Change-Number: 87860 Gerrit-PatchSet: 3 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Update flash layout
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/87860?usp=email ) Change subject: mb/google/fatcat: Update flash layout ...................................................................... Patch Set 2: (5 comments) Patchset: PS1: > please measure the boot time between AP FW w/ RW-A and RW-B . […] Acknowledged File src/mainboard/google/fatcat/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/87860/comment/07f90b72_e629ee0d?us… : PS1, Line 6: SI_BIOS 23M { > please refer from this […] Acknowledged https://review.coreboot.org/c/coreboot/+/87860/comment/b806face_dca55f4a?us… : PS1, Line 7: 8M > > As Bora reported that w/ 7680K, build is still failing, I changed it to 8M. I will check once. […] Acknowledged https://review.coreboot.org/c/coreboot/+/87860/comment/3edc7421_f44176cc?us… : PS1, Line 17: 8M > 7680K Acknowledged https://review.coreboot.org/c/coreboot/+/87860/comment/bedca0ba_caaa98bf?us… : PS1, Line 36: 1M > RW_UNUSED 2M Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c Gerrit-Change-Number: 87860 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 May 2025 19:17:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Update flash layout
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/87860?usp=email ) Change subject: mb/google/fatcat: Update flash layout ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c Gerrit-Change-Number: 87860 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 29 May 2025 19:16:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: ec/google: Add support for Realtek EC in ChromeOS EC
by Chao Jhan Bo (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jon Murphy, Karthik Ramasubramanian, Keith Short, Paul Menzel, Subrata Banik. Chao Jhan Bo has posted comments on this change by Chao Jhan Bo. ( https://review.coreboot.org/c/coreboot/+/87544?usp=email ) Change subject: ec/google: Add support for Realtek EC in ChromeOS EC ...................................................................... Patch Set 21: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/87544/comment/14126894_481a3c27?us… : PS18, Line 23: chipset_read_bytes > The `chipset_read_bytes()` and `chipset_write_bytes()` implementations for both MEC and RTK are inco […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Gerrit-Change-Number: 87544 Gerrit-PatchSet: 21 Gerrit-Owner: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 29 May 2025 19:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Short <keithshort(a)chromium.org>

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