May 2025 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[main]: mb/google/trulo/var/pujjocento: Configure USB related settings
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87834?usp=email ) Change subject: mb/google/trulo/var/pujjocento: Configure USB related settings ...................................................................... mb/google/trulo/var/pujjocento: Configure USB related settings Modify USB related settings according to the proto schematic diagram. BUG=b:409254508 BRANCH=none TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok. Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjocento/overridetree.cb 1 file changed, 51 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index e362c2d..517d210 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -42,15 +42,15 @@ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch) register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch) - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch) + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A MB (6.4 inch) + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A DB (6.2 inch) register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch) register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB)) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3 Type-A port A1(DB) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" @@ -157,7 +157,6 @@ }" device domain 0 on - device ref igpu on end device ref dtt on chip drivers/intel/dptf ## sensor information @@ -323,6 +322,43 @@ end end end + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + # Internal panel on the first port of the graphics chip + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on @@ -330,14 +366,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end end @@ -350,28 +386,28 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on end end chip drivers/usb/acpi @@ -406,14 +442,14 @@ register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi @@ -632,7 +668,6 @@ device pnp 0c09.0 on end end end - device ref pmc hidden end device ref hda on chip drivers/sof register "spkr_tplg" = "max98360a" -- To view, visit https://review.coreboot.org/c/coreboot/+/87834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e Gerrit-Change-Number: 87834 Gerrit-PatchSet: 5 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/bluey: Implement board and SKU ID retrieval
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87861?usp=email ) Change subject: mb/google/bluey: Implement board and SKU ID retrieval ...................................................................... mb/google/bluey: Implement board and SKU ID retrieval This commit populates the `board_id()` and `sku_id()` functions for the Google Bluey mainboard, replacing the previous placeholder implementations. - The Board ID (`board_id()`) is now determined by reading a set of four GPIO pins (GPIO138 as MSB, GPIO137, GPIO136, GPIO135 as LSB) and interpreting their states as a base-3 encoded value using the `gpio_base3_value()` helper. - The SKU ID (`sku_id()`) is retrieved from the Google ChromeEC by calling `google_chromeec_get_board_sku()` when a ChromeEC is configured (`CONFIG(EC_GOOGLE_CHROMEEC)`). Both ID values are cached after their initial determination to avoid redundant reads. BUG=b:404985109 TEST=Able to build google/bluey Change-Id: Ic5a084e35b33a82fef76f33c2663aba7a48c16a7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87861 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/bluey/boardid.c 1 file changed, 20 insertions(+), 2 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/bluey/boardid.c b/src/mainboard/google/bluey/boardid.c index b529ff1..c893fdb 100644 --- a/src/mainboard/google/bluey/boardid.c +++ b/src/mainboard/google/bluey/boardid.c @@ -1,17 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> uint32_t board_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - /* Placeholder */ + if (id != UNDEFINED_STRAPPING_ID) + return id; + + const gpio_t pins[] = { + [3] = GPIO(138), + [2] = GPIO(137), + [1] = GPIO(136), + [0] = GPIO(135) + }; + + id = gpio_base3_value(pins, ARRAY_SIZE(pins)); + return id; } uint32_t sku_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - /* Placeholder */ + if (id != UNDEFINED_STRAPPING_ID) + return id; + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = google_chromeec_get_board_sku(); + return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5a084e35b33a82fef76f33c2663aba7a48c16a7 Gerrit-Change-Number: 87861 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/bluey: Add WLAN and SSD PCI devices to devicetree
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87859?usp=email ) Change subject: mb/google/bluey: Add WLAN and SSD PCI devices to devicetree ...................................................................... mb/google/bluey: Add WLAN and SSD PCI devices to devicetree This commit updates the devicetree for the Google Bluey mainboard to include entries for the WLAN and SSD PCI devices. These devices are located on the x1p42100 SoC's PCI domain 0: - WLAN: device pci 04.0 - SSD: device pci 06.0 BUG=b:404985109 TEST=Able to build google/bluey. Change-Id: If0a9491f4178ee9a44c04aea1330b6522dfd9bf0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87859 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/bluey/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/bluey/devicetree.cb b/src/mainboard/google/bluey/devicetree.cb index 7aed490..69d0533 100644 --- a/src/mainboard/google/bluey/devicetree.cb +++ b/src/mainboard/google/bluey/devicetree.cb @@ -3,5 +3,7 @@ chip soc/qualcomm/x1p42100 device cpu_cluster 0 on end device domain 0 on + device pci 04.0 on end # WLAN + device pci 06.0 on end # SSD end end -- To view, visit https://review.coreboot.org/c/coreboot/+/87859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0a9491f4178ee9a44c04aea1330b6522dfd9bf0 Gerrit-Change-Number: 87859 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/qualcomm/x1p42100: Enable basic PCIe support
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87858?usp=email ) Change subject: soc/qualcomm/x1p42100: Enable basic PCIe support ...................................................................... soc/qualcomm/x1p42100: Enable basic PCIe support This commit introduces initial support for PCI Express on the Qualcomm x1p42100 SoC. Key changes include: - Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem support for this SoC. - Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this platform will not use the standard MMCONFIG ECAM for PCI configuration space access. An alternative mechanism will be required. - Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI` is enabled, incorporating common PCIe helper functions. BUG=b:404985109 TEST=Able to build google/bluey. Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87858 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/x1p42100/Kconfig M src/soc/qualcomm/x1p42100/Makefile.mk 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Pranava Y N: Looks good to me, approved diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig index 52f270b..d9d6a93 100644 --- a/src/soc/qualcomm/x1p42100/Kconfig +++ b/src/soc/qualcomm/x1p42100/Kconfig @@ -21,6 +21,8 @@ select HAVE_UART_SPECIAL select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select PCI + select NO_ECAM_MMCONF_SUPPORT select SDHCI_CONTROLLER select SOC_QUALCOMM_COMMON diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk index 0135f9b..f75fdd4 100644 --- a/src/soc/qualcomm/x1p42100/Makefile.mk +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -38,6 +38,7 @@ ramstage-y += soc.c ramstage-y += cbmem.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-$(CONFIG_PCI) += ../common/pcie_common.c ramstage-y += cpucp_load_reset.c ################################################################################ -- To view, visit https://review.coreboot.org/c/coreboot/+/87858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1 Gerrit-Change-Number: 87858 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87857?usp=email ) Change subject: soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init ...................................................................... soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init This commit introduces `bootblock_soc_early_init` API for early SoC initialization sequence in the bootblock. - `bootblock_soc_early_init()`: This function now handles very early initialization steps (before console init), specifically `soc_mmu_init()` when the bootblock is not compressed. - `bootblock_soc_init()`: This function retains the subsequent initialization tasks including `clock_init()`, `quadspi_init()`, and `qupv3_fw_init()`. This change ensures MMU setup to occur before other peripheral and clock initializations. TEST=Able to get bootblock console log in proper. Change-Id: I8bbcdb9c39e13fac81ef6a34647c4f343a619561 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87857 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/qualcomm/x1p42100/bootblock.c 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c index c6d8b9e..d106912 100644 --- a/src/soc/qualcomm/x1p42100/bootblock.c +++ b/src/soc/qualcomm/x1p42100/bootblock.c @@ -7,11 +7,15 @@ #define SPI_BUS_CLOCK_FREQ (50 * MHz) +void bootblock_soc_early_init(void) +{ + if (!CONFIG(COMPRESS_BOOTBLOCK)) + soc_mmu_init(); +} + void bootblock_soc_init(void) { clock_init(); - if (!CONFIG(COMPRESS_BOOTBLOCK)) - soc_mmu_init(); quadspi_init(SPI_BUS_CLOCK_FREQ); qupv3_fw_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/87857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bbcdb9c39e13fac81ef6a34647c4f343a619561 Gerrit-Change-Number: 87857 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/qualcomm/x1p42100: Add placeholder for early clock initialization
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87850?usp=email ) Change subject: soc/qualcomm/x1p42100: Add placeholder for early clock initialization ...................................................................... soc/qualcomm/x1p42100: Add placeholder for early clock initialization This commit adds the `clock_init()` function for the Qualcomm x1p42100 SoC. This function is now called at the beginning of `bootblock_soc_init()` to enable SoC-specific clock setup early in the boot process. The `clock_init()` function definition is currently a placeholder and will be populated with the required clock configurations in subsequent changes. BUG=b:404985109 TEST=Able to build google/bluey Change-Id: Ifb856ea4132def9cd3a36b081d24037a1a4efaba Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87850 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/x1p42100/bootblock.c M src/soc/qualcomm/x1p42100/clock.c M src/soc/qualcomm/x1p42100/include/soc/clock.h 3 files changed, 7 insertions(+), 0 deletions(-) Approvals: Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c index 32a958b..c6d8b9e 100644 --- a/src/soc/qualcomm/x1p42100/bootblock.c +++ b/src/soc/qualcomm/x1p42100/bootblock.c @@ -9,6 +9,7 @@ void bootblock_soc_init(void) { + clock_init(); if (!CONFIG(COMPRESS_BOOTBLOCK)) soc_mmu_init(); diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c index 9a4b16d..5e9706f 100644 --- a/src/soc/qualcomm/x1p42100/clock.c +++ b/src/soc/qualcomm/x1p42100/clock.c @@ -16,3 +16,8 @@ { /* placeholder */ } + +void clock_init(void) +{ + /* placeholder */ +} diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h index c6b01f8..bb32770 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/clock.h +++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h @@ -37,6 +37,7 @@ }; /* TODO: update as per datasheet */ +void clock_init(void); void clock_configure_qspi(uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); -- To view, visit https://review.coreboot.org/c/coreboot/+/87850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb856ea4132def9cd3a36b081d24037a1a4efaba Gerrit-Change-Number: 87850 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/panterlake: avoid SPI access delay
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Wonkyu Kim. Subrata Banik has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87739?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/panterlake: avoid SPI access delay ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87739/comment/1fdef906_2f46587f?us… : PS14, Line 12: TEST TEST= -- To view, visit https://review.coreboot.org/c/coreboot/+/87739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e Gerrit-Change-Number: 87739 Gerrit-PatchSet: 14 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 May 2025 04:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/panterlake: avoid SPI access delay
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Wonkyu Kim. Subrata Banik has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87739?usp=email ) Change subject: soc/intel/panterlake: avoid SPI access delay ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e Gerrit-Change-Number: 87739 Gerrit-PatchSet: 14 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 May 2025 04:20:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: elog: Handle elog in later boot phase
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, Wonkyu Kim. Subrata Banik has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87740?usp=email ) Change subject: elog: Handle elog in later boot phase ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896 Gerrit-Change-Number: 87740 Gerrit-PatchSet: 15 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 May 2025 04:20:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: security/vboot: Back up CMOS data later boot phase
by Subrata Banik (Code Review) May 29, 2025

May 29, 2025

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Wonkyu Kim, Yu-Ping Wu. Subrata Banik has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87738?usp=email ) Change subject: security/vboot: Back up CMOS data later boot phase ...................................................................... Patch Set 21: Code-Review+1 (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/87738/comment/671a58b3_e577521e?us… : PS21, Line 1575: SOCs nit ``` SoCs ``` https://review.coreboot.org/c/coreboot/+/87738/comment/14465eef_1cbb7e1c?us… : PS21, Line 1575: lake nit ``` Lake ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/87738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8836c14601beb56c614605b9840c8506d6d8536c Gerrit-Change-Number: 87738 Gerrit-PatchSet: 21 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 30 May 2025 04:20:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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