May 2025 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B
by Paul Menzel (Code Review) May 30, 2025

May 30, 2025

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/87900?usp=email ) Change subject: mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87900/comment/85d36f0e_7e6f9c57?us… : PS1, Line 9: Changes for DDI-B, GPP_A18/DDSP_HPDB, GPP_H15/DDPB_CTRLCLK, : GPP_H17/DDPB_CTRLDATA Please make it a sentence, and also mention the source. -- To view, visit https://review.coreboot.org/c/coreboot/+/87900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61ef761df7936fb42d4fe68a2b5cd2fa649b7b33 Gerrit-Change-Number: 87900 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 May 2025 09:31:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8189: Add spm_firmware.bin version 2.0
by Paul Menzel (Code Review) May 30, 2025

May 30, 2025

Attention is currently required from: Vince Liu. Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/blobs/+/87902?usp=email ) Change subject: soc/mediatek/mt8189: Add spm_firmware.bin version 2.0 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/87902/comment/9022d088_cb422f63?usp=e… : PS1, Line 13: TEST=SPM bootup pass Please document, if and how suspend/resume was tested. -- To view, visit https://review.coreboot.org/c/blobs/+/87902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ia88e896245207f6184238ede0cd6f49378a0106a Gerrit-Change-Number: 87902 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 May 2025 09:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8189: Add SSPM firmware v2.0
by Paul Menzel (Code Review) May 30, 2025

May 30, 2025

Attention is currently required from: Vince Liu. Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/blobs/+/87901?usp=email ) Change subject: soc/mediatek/mt8189: Add SSPM firmware v2.0 ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/blobs/+/87901/comment/bdb2b0b5_27f5cf26?usp=e… : PS1, Line 9: Update sspm.bin for support suspend/resume feature. Mention AOC? https://review.coreboot.org/c/blobs/+/87901/comment/f013587a_7d4f4a06?usp=e… : PS1, Line 13: TEST=SSPM bootup pass How did you check AOC suspend/resume? Any log messages? -- To view, visit https://review.coreboot.org/c/blobs/+/87901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I76c6fe54639aa660db8ce99a3be67880bf8cad3c Gerrit-Change-Number: 87901 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Fri, 30 May 2025 09:30:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8189: Add spm_firmware.bin version 2.0
by Vince Liu (Code Review) May 30, 2025

May 30, 2025

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/87902?usp=email ) Change subject: soc/mediatek/mt8189: Add spm_firmware.bin version 2.0 ...................................................................... soc/mediatek/mt8189: Add spm_firmware.bin version 2.0 Update SPM firmware to support suspend/resume function. BUG=b:379008996 BRANCH=none TEST=SPM bootup pass Change-Id: Ia88e896245207f6184238ede0cd6f49378a0106a Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8189/spm_firmware.bin M soc/mediatek/mt8189/spm_firmware.bin.md5 M soc/mediatek/mt8189/spm_release_notes.txt 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/02/87902/1 diff --git a/soc/mediatek/mt8189/spm_firmware.bin b/soc/mediatek/mt8189/spm_firmware.bin index 266627f..9443d80 100644 --- a/soc/mediatek/mt8189/spm_firmware.bin +++ b/soc/mediatek/mt8189/spm_firmware.bin Binary files differ diff --git a/soc/mediatek/mt8189/spm_firmware.bin.md5 b/soc/mediatek/mt8189/spm_firmware.bin.md5 index 849d353..447d2b2 100644 --- a/soc/mediatek/mt8189/spm_firmware.bin.md5 +++ b/soc/mediatek/mt8189/spm_firmware.bin.md5 @@ -1 +1 @@ -7515b926bc507c2d9e55cc03c0aa58ba *spm_firmware.bin +31ff9acd31e359fbe014aed2650ea0ee *spm_firmware.bin diff --git a/soc/mediatek/mt8189/spm_release_notes.txt b/soc/mediatek/mt8189/spm_release_notes.txt index f3b09fd..299bea0 100644 --- a/soc/mediatek/mt8189/spm_release_notes.txt +++ b/soc/mediatek/mt8189/spm_release_notes.txt @@ -1,4 +1,7 @@ ** Build from MediaTek Internal ** +# Version 2.0 +1. Support suspend/resume function. + # Version 1.0 1. Initial release. -- To view, visit https://review.coreboot.org/c/blobs/+/87902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ia88e896245207f6184238ede0cd6f49378a0106a Gerrit-Change-Number: 87902 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8189: Add SSPM firmware v2.0
by Vince Liu (Code Review) May 30, 2025

May 30, 2025

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/87901?usp=email ) Change subject: soc/mediatek/mt8189: Add SSPM firmware v2.0 ...................................................................... soc/mediatek/mt8189: Add SSPM firmware v2.0 Update sspm.bin for support suspend/resume feature. BUG=b:379008996 BRANCH=none TEST=SSPM bootup pass Change-Id: I76c6fe54639aa660db8ce99a3be67880bf8cad3c Signed-off-by: Hailong Fan <hailong.fan(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8189/sspm.bin M soc/mediatek/mt8189/sspm.bin.md5 M soc/mediatek/mt8189/sspm_release_notes.txt 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/01/87901/1 diff --git a/soc/mediatek/mt8189/sspm.bin b/soc/mediatek/mt8189/sspm.bin index f76ffb6..bd84cae 100644 --- a/soc/mediatek/mt8189/sspm.bin +++ b/soc/mediatek/mt8189/sspm.bin Binary files differ diff --git a/soc/mediatek/mt8189/sspm.bin.md5 b/soc/mediatek/mt8189/sspm.bin.md5 index 229897b..d709de1 100644 --- a/soc/mediatek/mt8189/sspm.bin.md5 +++ b/soc/mediatek/mt8189/sspm.bin.md5 @@ -1 +1 @@ -d71c284eeac8152698b07938fd9f3648 *sspm.bin +d009bf8ebd913be709807ae88f7ca388 *sspm.bin diff --git a/soc/mediatek/mt8189/sspm_release_notes.txt b/soc/mediatek/mt8189/sspm_release_notes.txt index f3b09fd..9a8d18c 100644 --- a/soc/mediatek/mt8189/sspm_release_notes.txt +++ b/soc/mediatek/mt8189/sspm_release_notes.txt @@ -1,4 +1,7 @@ ** Build from MediaTek Internal ** +# Version 2.0 +1. Support AOC feature in suspend/resume scenarios. + # Version 1.0 1. Initial release. -- To view, visit https://review.coreboot.org/c/blobs/+/87901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I76c6fe54639aa660db8ce99a3be67880bf8cad3c Gerrit-Change-Number: 87901 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B
by Kun Liu (Code Review) May 30, 2025

May 30, 2025

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87900?usp=email ) Change subject: mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B ...................................................................... mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B Changes for DDI-B, GPP_A18/DDSP_HPDB, GPP_H15/DDPB_CTRLCLK, GPP_H17/DDPB_CTRLDATA BUG=b:409254508 BRANCH=none TEST=emerge-nissa coreboot chromeos-bootimage. Change-Id: I61ef761df7936fb42d4fe68a2b5cd2fa649b7b33 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjocento/gpio.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/87900/1 diff --git a/src/mainboard/google/brya/variants/pujjocento/gpio.c b/src/mainboard/google/brya/variants/pujjocento/gpio.c index ea8d9bb..3df21e7 100644 --- a/src/mainboard/google/brya/variants/pujjocento/gpio.c +++ b/src/mainboard/google/brya/variants/pujjocento/gpio.c @@ -38,12 +38,12 @@ PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), /* A17 : NC */ PAD_NC(GPP_A17, NONE), - /* A18 : NC */ - PAD_NC(GPP_A18, NONE), + /* A18 : NC ==> HDMI_HPD_SRC*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : NC */ PAD_NC(GPP_A19, NONE), - /* A20 : DDSP_HPD2 ==> SOC_HDMI_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ @@ -198,10 +198,10 @@ PAD_NC(GPP_E18, NONE), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ PAD_NC(GPP_E19, NONE), - /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61ef761df7936fb42d4fe68a2b5cd2fa649b7b33 Gerrit-Change-Number: 87900 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from FSP 3144_01 to FSP 3182_01
by Alok Agarwal (Code Review) May 30, 2025

May 30, 2025

Attention is currently required from: srinivas.kulkarni(a)intel.com. Alok Agarwal has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/87879?usp=email ) Change subject: vc/intel/fsp/ptl: Update header files from FSP 3144_01 to FSP 3182_01 ...................................................................... Patch Set 4: (4 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/87879/comment/ab111e68_5e5562b7?us… : PS4, Line 7: > Remove space here Done https://review.coreboot.org/c/coreboot/+/87879/comment/470884b6_ac2f0469?us… : PS4, Line 7: mtl > Please update the platform correctly Done https://review.coreboot.org/c/coreboot/+/87879/comment/0d14a0a2_f6fc01bd?us… : PS4, Line 14: > Remove space here Done https://review.coreboot.org/c/coreboot/+/87879/comment/f8fc33fa_b9b03701?us… : PS4, Line 16: NTU > Add bug#421287370 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14e8c3c8751ae6aa0718d0015a1611ced6a2cdd4 Gerrit-Change-Number: 87879 Gerrit-PatchSet: 4 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Fri, 30 May 2025 08:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: srinivas.kulkarni(a)intel.com

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port
by hualin wei (Code Review) May 30, 2025

May 30, 2025

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Subrata Banik. hualin wei has posted comments on this change by Jianeng Ceng. ( https://review.coreboot.org/c/coreboot/+/87899?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Gerrit-Change-Number: 87899 Gerrit-PatchSet: 1 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 May 2025 05:33:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port
by Jianeng Ceng (Code Review) May 30, 2025

May 30, 2025

Jianeng Ceng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87899?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port ...................................................................... mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds to TCSS port0. In order for the DP functions of the two Type-C ports to operate normally, the corresponding relationship needs to be configured correctly. BUG=b:418106736 TEST=DP function of Type-C0/C1 workable Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoniru/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/87899/1 diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb index 60d3117..cc3d1dc 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb @@ -27,12 +27,12 @@ # motherboard to USBC connector register "tcss_aux_ori" = "5" - register "typec_aux_bias_pads[0]" = "{ + register "typec_aux_bias_pads[1]" = "{ .pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23 }" - register "typec_aux_bias_pads[1]" = "{ + register "typec_aux_bias_pads[0]" = "{ .pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22 }" -- To view, visit https://review.coreboot.org/c/coreboot/+/87899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Gerrit-Change-Number: 87899 Gerrit-PatchSet: 1 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/trulo/var/pujjocento: Configure USB related settings
by Subrata Banik (Code Review) May 30, 2025

May 30, 2025

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87834?usp=email ) Change subject: mb/google/trulo/var/pujjocento: Configure USB related settings ...................................................................... mb/google/trulo/var/pujjocento: Configure USB related settings Modify USB related settings according to the proto schematic diagram. BUG=b:409254508 BRANCH=none TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok. Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjocento/overridetree.cb 1 file changed, 51 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index e362c2d..517d210 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -42,15 +42,15 @@ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch) register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch) - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch) + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A MB (6.4 inch) + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A DB (6.2 inch) register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch) register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB)) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3 Type-A port A1(DB) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" @@ -157,7 +157,6 @@ }" device domain 0 on - device ref igpu on end device ref dtt on chip drivers/intel/dptf ## sensor information @@ -323,6 +322,43 @@ end end end + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + # Internal panel on the first port of the graphics chip + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on @@ -330,14 +366,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end end @@ -350,28 +386,28 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on end end chip drivers/usb/acpi @@ -406,14 +442,14 @@ register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi @@ -632,7 +668,6 @@ device pnp 0c09.0 on end end end - device ref pmc hidden end device ref hda on chip drivers/sof register "spkr_tplg" = "max98360a" -- To view, visit https://review.coreboot.org/c/coreboot/+/87834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e Gerrit-Change-Number: 87834 Gerrit-PatchSet: 5 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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