May 2025 - coreboot-gerrit - mail.coreboot.org

[L] Change in coreboot[main]: mb/asus/h61-series: Add H61M-A/USB3
by Alicja Michalska (Code Review) May 1, 2025

May 1, 2025

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Felix Singer, Maximilian Brune, Patrick Rudolph. Alicja Michalska has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/86726?usp=email ) Change subject: mb/asus/h61-series: Add H61M-A/USB3 ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: LGTM, is it a similar problem to IT8613E or are we just missing datasheet to implement the missing functionality? -- To view, visit https://review.coreboot.org/c/coreboot/+/86726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18b116d265e0b7105e13a317b552aab0e4bbc762 Gerrit-Change-Number: 86726 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 01 May 2025 02:03:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
by Zhixing Ma (Code Review) May 1, 2025

May 1, 2025

Attention is currently required from: Avi Uday, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Zhixing Ma has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/87505?usp=email ) Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7 Gerrit-Change-Number: 87505 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 01 May 2025 00:43:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/apollolake/acpi: Add function to get PCIe BAR
by Matt DeVillier (Code Review) May 1, 2025

May 1, 2025

Attention is currently required from: Intel coreboot Reviewers, Matt DeVillier, Sean Rhodes. Hello Intel coreboot Reviewers, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87486?usp=email to look at the new patch set (#3). Change subject: soc/intel/apollolake/acpi: Add function to get PCIe BAR ...................................................................... soc/intel/apollolake/acpi: Add function to get PCIe BAR Commit 12abfb43dc0a ("soc/intel/cnvi: Add CNVW OpRegion") added an ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC common northbridge.asl, but not in the Apollolake northbridge.asl. Add the missing GPCB function to the APL northbridge. Per Intel doc 336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms. TEST=build/boot google/ampton, verify no ACPI errors in dmesg related to missing function/object, Windows boots without BSOD. Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/acpi/northbridge.asl 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87486/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87486?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Gerrit-Change-Number: 87486 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/apollolake/acpi: Add function to get PCIe BAR
by Matt DeVillier (Code Review) May 1, 2025

May 1, 2025

Attention is currently required from: Intel coreboot Reviewers, Matt DeVillier, Sean Rhodes. Hello Intel coreboot Reviewers, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87486?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Sean Rhodes, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/apollolake/acpi: Add function to get PCIe BAR ...................................................................... soc/intel/apollolake/acpi: Add function to get PCIe BAR Commit 12abfb43dc0a ("soc/intel/cnvi: Add CNVW OpRegion") added an ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC common northbridge.asl, but not in the Apollolake northbridge.asl. Add the missing GPCB function to the APL northbridge. Per Intel doc TEST=build/boot google/ampton, verify no ACPI errors in dmesg related to missing function/object, Windows boots without BSOD. Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/acpi/northbridge.asl 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87486/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87486?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Gerrit-Change-Number: 87486 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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