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Change subject: nb/via/cx700: Perform early bootblock init
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82768/comment/1e1f1691_40b32e58?us… :
PS2, Line 9: Disable a timer (GP3) that is always running by default. And enable
> What does GP3 do if not disabled?
Angel,
have you thé answer?
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Change subject: mb/google/brya/var/trulo: Update PL1 and enable Charger device
......................................................................
mb/google/brya/var/trulo: Update PL1 and enable Charger device
Update the RAPL PL1 limit and MMIO PL1 max values as per silicon TDP.
Update the TSR1 target's source to CHARGER in Passive Policy.
BUG=b:378623372
TEST=Build and boot on Trulo board. Verified PL1 value is updated in DTT and sysfs interfaces. Also verified the source for TSR1 is updated to Charger in Passive Policy
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 6 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85184/3
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Change subject: mb/google/brya/var/trulo: Enable Charger cooling device; Set correct PL1 values as per silicon TDP
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Set Ready For Review
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Change subject: mb/google/nissa/var/pujjoga: Turn off camera during S0ix
......................................................................
Patch Set 9: Code-Review+2
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Change subject: mb/google/nissa/var/pujjoga: Turn off camera during S0ix
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/brya/variants/pujjoga/variant.c:
https://review.coreboot.org/c/coreboot/+/85133/comment/dbd028bc_766fa119?us… :
PS8, Line 9: #include <delay.h>
> no need.
Done. Thanks.
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Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................
soc/intel/ptl: Define GPE1 macros and register fields
New GPE1 bits are introduced in PTL for internal devices, including
PME_B0, hot plug, and PCIe events.
defines for GPE number for additional STD GPE0 in PTL
defines for GPE number for GPE1
defines for GPE1 bits
SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is selected
NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits.
BUG=362310295
TEST=This cannot be tested directly.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/include/soc/gpe.h
M src/soc/intel/pantherlake/include/soc/pm.h
3 files changed, 439 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/16
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