coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant
by Pranava Y N (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Subrata Banik. Pranava Y N has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85222?usp=email ) Change subject: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I977e72a6db99b40a79d37a1b8fe5bee5d98934c7 Gerrit-Change-Number: 85222 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 08:46:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant
by Jayvik Desai (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85222?usp=email ) Change subject: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/85222/comment/72372c58_f4b749a9?us… : PS2, Line 78: #if !CONFIG(BOARD_GOOGLE_FATCAT) || !CONFIG(BOARD_GOOGLE_FATCATISH) > +1 Yes that was incorrect, updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/85222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I977e72a6db99b40a79d37a1b8fe5bee5d98934c7 Gerrit-Change-Number: 85222 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 08:44:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/skx/ioapic.c: https://review.coreboot.org/c/coreboot/+/85170/comment/3f01fa51_51b097b7?us… : PS2, Line 35: register_new_ioapic(resource->base); > Should we use ioapic_get_max_vectors instead of 32 here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 08:41:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85139?usp=email ) Change subject: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/85139/comment/372471e8_35f81f95?us… : PS1, Line 535: PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)); > Should we continue on !dev here? (though theoretically this is not possible) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b Gerrit-Change-Number: 85139 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 08:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: arch/x86: Enable support for IOAPIC devices
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85226?usp=email ) Change subject: arch/x86: Enable support for IOAPIC devices ...................................................................... arch/x86: Enable support for IOAPIC devices On platforms with multiple IOAPICs the GSI base must not be linear, which is currently assumed by acpi_create_madt_ioapic_from_hw(). Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices into the MADT table if any. For now, since no platform adds IOAPIC devices, the existing behaviour remains the same. Allows to get rid of soc_get_ioapic_info(). Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi_apic.c M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/device/device_const.c M src/include/device/path.h 5 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85226/1 diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index fe0459b..bd78056 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> @@ -226,6 +227,8 @@ unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current) { + struct device *dev = NULL; + madt->lapic_addr = cpu_get_lapic_addr(); if (CONFIG(ACPI_HAVE_PCAT_8259)) @@ -237,5 +240,15 @@ if (CONFIG(ACPI_COMMON_MADT_IOAPIC)) current = acpi_create_madt_ioapic_gsi0_default(current); + while ((dev = dev_find_path(dev, DEVICE_PATH_IOAPIC)) != NULL) { + assert(!CONFIG(ACPI_COMMON_MADT_IOAPIC) || dev->path.ioapic.gsi_base != 0); + assert(dev->path.ioapic.addr); + + current += acpi_create_madt_ioapic((void *)(uintptr_t)current, + dev->path.ioapic.ioapic_id, + dev->path.ioapic.addr, + dev->path.ioapic.gsi_base); + } + return current; } diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 530128a..6c19ed0 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -16,6 +16,9 @@ void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count); void ioapic_lock_max_vectors(uintptr_t ioapic_base); +struct device *ioapic_create_dev(struct device *parent, + const uintptr_t ioapic_base, + const u32 gsi_base); void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id); void register_new_ioapic(uintptr_t ioapic_base); void register_new_ioapic_gsi0(uintptr_t ioapic_base); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 5bb2adb5..b9487d6 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <device/device.h> #include <device/mmio.h> #include <arch/ioapic.h> #include <console/console.h> @@ -174,6 +175,47 @@ } } +/** + * Create a new IOAPIC device under the given device. + * + * @param parent The parent device. A PCI domain or PCI device (in case of PCI IOAPIC). + * @param ioapic_base The IOAPIC base address + * @param gsi_base Platform specific GSI base + * @return Pointer to the device struct. + */ +struct device *ioapic_create_dev(struct device *parent, + const uintptr_t ioapic_base, + const u32 gsi_base) +{ + struct device dummy; + struct device *dev; + + if (!parent) + return NULL; + + struct bus *bus = alloc_bus(parent); + if (!bus) + return NULL; + + memset(&dummy, 0, sizeof(dummy)); + + if (gsi_base == 0) + register_new_ioapic_gsi0(ioapic_base); + else + register_new_ioapic(ioapic_base); + + dummy.upstream = bus; + dummy.path.type = DEVICE_PATH_IOAPIC; + dummy.path.ioapic.ioapic_id = get_ioapic_id(ioapic_base); + dummy.path.ioapic.addr = ioapic_base; + dummy.path.ioapic.gsi_base = gsi_base; + + dev = alloc_dev(bus, &dummy.path); + assert(dev); + + return dev; +} + void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); @@ -192,4 +234,4 @@ ioapic_id++; set_ioapic_id(ioapic_base, ioapic_id); clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); -} +} \ No newline at end of file diff --git a/src/device/device_const.c b/src/device/device_const.c index 9f3443e..2aef907 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -130,6 +130,9 @@ case DEVICE_PATH_CPU_BUS: equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; + case DEVICE_PATH_IOAPIC: + equal = (path1->ioapic.ioapic_id == path2->ioapic.ioapic_id); + break; case DEVICE_PATH_GENERIC: equal = (path1->generic.id == path2->generic.id) && (path1->generic.subid == path2->generic.subid); diff --git a/src/include/device/path.h b/src/include/device/path.h index d8ef880..8e9ec3b 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -85,7 +85,9 @@ }; struct ioapic_path { + uintptr_t addr; unsigned int ioapic_id; + unsigned int gsi_base; }; struct cpu_cluster_path { -- To view, visit https://review.coreboot.org/c/coreboot/+/85226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3 Gerrit-Change-Number: 85226 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Hello Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85170?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... soc/intel/xeon_sp/skx: Configure IOAPICs FSP only configures the PCH IOAPIC. Let coreboot reconfigure all IOAPICs to assign unique IDs to each. The IOAPICs on Socket1 start at GSI 72, thus calculate the excat GSI address for each IOAPIC instead of assume it's a linear address space. Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info() from advertising wrong GSI addresses. TEST: Booted on ocp/tiogapass with correct GSI bases asigned matching the _PRT advertised GSI bases. Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/lpc_gen1.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk A src/soc/intel/xeon_sp/skx/ioapic.c 4 files changed, 76 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85139?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR ...................................................................... soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR On 1st and 2nd gen Xeon-SP the VTD PCI device has different PCI IDs, depending if it's on the CSTACK or PSTACK. Make sure to handle all VTD device on all stacks the same. For later SoCs this was already the case since the PCI devices have the same PCI ID. Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/gnr/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c 4 files changed, 34 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85139/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b Gerrit-Change-Number: 85139 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant
by Jayvik Desai (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Jayvik Desai, Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85222?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant ...................................................................... mb/google/fatcat: Add EC_SYNC_IRQ and GPIO_PCH_WP for fatcat_ish variant This commit adds the EC_SYNC_IRQ and GPIO_PCH_WP macros for the fatcat_ish variant. BUG=b:370984186 TEST=able to build fatcat/fatcat_ish w/o any error. Change-Id: I977e72a6db99b40a79d37a1b8fe5bee5d98934c7 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85222/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I977e72a6db99b40a79d37a1b8fe5bee5d98934c7 Gerrit-Change-Number: 85222 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Fix SRAT debug prints
by Patrick Rudolph (Code Review) 21 Nov '24

21 Nov '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85189?usp=email ) Change subject: soc/intel/xeon_sp: Fix SRAT debug prints ...................................................................... soc/intel/xeon_sp: Fix SRAT debug prints - Drop duplicated fields - Drop fields filled with constant values - Drop SRAT prefix for sysmemmap entries - Print all zeros when concatenating two hex numbers Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85189 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 2d0baf9..b64271e 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -84,9 +84,9 @@ addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); - printk(BIOS_DEBUG, "SRAT: sysmemmap addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, type: %d, reserved: %d\n", addr, e->BaseAddress, - size, e->ElementSize, e->Type, is_memtype_reserved(e->Type)); + printk(BIOS_DEBUG, " sysmemmap addr: 0x%llx, size: 0x%llx, " + "type: %d, reserved: %d\n", addr, size, e->Type, + is_memtype_reserved(e->Type)); /* skip reserved memory region */ if (is_memtype_reserved(e->Type)) @@ -122,9 +122,9 @@ } if (!skip) { - printk(BIOS_DEBUG, "SRAT: adding memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - *cnt, srat.length, srat.base_address_high, srat.base_address_low, + printk(BIOS_DEBUG, "SRAT: memory %d: addr=0x%x%08x, " + "length=0x%x%08x, proximity_domain=%d, flags=%x\n", + *cnt, srat.base_address_high, srat.base_address_low, srat.length_high, srat.length_low, srat.proximity_domain, srat.flags); memcpy(current, &srat, sizeof(acpi_srat_mem_t)); -- To view, visit https://review.coreboot.org/c/coreboot/+/85189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b Gerrit-Change-Number: 85189 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: mb/google/fatcat: Refactor EC_SOC_INT_ODL GPP for fatcat_ish variant
by Kapil Porwal (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Jayvik Desai, Subrata Banik. Kapil Porwal has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85223?usp=email ) Change subject: mb/google/fatcat: Refactor EC_SOC_INT_ODL GPP for fatcat_ish variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88bd76b2110b4c0742569f1ccb2030ea516b3782 Gerrit-Change-Number: 85223 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 08:32:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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