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Change subject: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
......................................................................
Patch Set 5: Code-Review+2
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, Vinay Kumar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brya/var/trulo: Update PL1 values as per silicon TDP
......................................................................
mb/google/brya/var/trulo: Update PL1 values as per silicon TDP
Update the RAPL PL1 limit and MMIO PL1 max values as per silicon TDP.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85184/4
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Change subject: mb/google/brya: Create uldrenite variant
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85207/comment/53449a6c_7bfd04b9?us… :
PS1, Line 9: Create the uldrenite variant of the brya reference board.
> How did you create the directory? Some script?
No, added manually.
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Change subject: mb/google/fatcat/var/francka: Change RAM_ID to 1
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85206/comment/1e813152_5a706567?us… :
PS1, Line 7: Change RAM_ID to 1
Maybe:
> Use RAM ID 1 for MT62F2G32D4DS-020 WT:F
https://review.coreboot.org/c/coreboot/+/85206/comment/338e0a3f_5d111fe5?us… :
PS1, Line 11:
Out of curiosity: What is the actual problem? Is 0 reserved for the empty SPD?
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Change subject: mb/google/nissa/var/pujjoga: Turn off camera during S0ix
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85133/comment/65427e85_5963b517?us… :
PS2, Line 11:
> This is not for the power saving. […]
Interesting. Please add that to the commit message.
https://review.coreboot.org/c/coreboot/+/85133/comment/f9dabf48_fc2c8bc9?us… :
PS2, Line 13: Ensure that camera is disabled during
: suspend and enabled during resume.
> We do the powerd_dbus_suspend and measure the camera power 3.3V which is disable. […]
Please add that to the commit message.
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Change subject: mb/google/brya/var/trulo: Update PL1 and enable Charger device
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85184/comment/01bf6c66_bf09ec25?us… :
PS3, Line 7: Update PL1 and enable Charger device
Please make it two commits.
https://review.coreboot.org/c/coreboot/+/85184/comment/4fc546f6_5f7e89ec?us… :
PS3, Line 13: TEST=Build and boot on Trulo board. Verified PL1 value is updated in DTT and sysfs interfaces. Also verified the source for TSR1 is updated to Charger in Passive Policy
Please re-flow for 72 characters per line.
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Change subject: soc/intel/cmn/acpi: Use Kconfig guards for UFS workarounds
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya: Create uldrenite variant
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85207/comment/ee215167_95e0982a?us… :
PS1, Line 9: Create the uldrenite variant of the brya reference board.
How did you create the directory? Some script?
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Change subject: soc/intel/pantherlake: Add option to enable UFS controller
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Patch Set 2: Code-Review+2
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