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Change subject: arch/x86: Enable support for IOAPIC devices
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Not sure if we need below fixes as well
void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id)
{
set_ioapic_id(ioapic_base, ioapic_id);
clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
-> only do this for ioapic_id == 0 case?
route_i8259_irq0(ioapic_base);
}
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Change subject: arch/x86: Enable support for IOAPIC devices
......................................................................
Patch Set 1:
(1 comment)
File src/arch/x86/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85226/comment/fd039110_d7025b69?us… :
PS1, Line 207: dummy.upstream = bus;
It looks like only the path is used, so we can skip the assignment of upstream here?
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, Vinay Kumar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
......................................................................
mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
The RAPL PL1 limit and MMIO PL1 max values should be set as per
silicon TDP (6W for N150/N250, 15W for N355).
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Output with 15W silicon as below:
cd /sys/class/powercap/
cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw
15000000
cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw
15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85184/5
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Change subject: mb/google/brya/var/trulo: Update PL1 values as per silicon TDP
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/trulo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85184/comment/72c452d6_0c997eaa?us… :
PS4, Line 184: register "power_limits_config[ADL_N_041_6W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 25,
: .tdp_pl4 = 78,
: }"
:
: register "power_limits_config[ADL_N_081_7W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 25,
: .tdp_pl4 = 78,
: }"
:
: register "power_limits_config[ADL_N_081_15W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 35,
: .tdp_pl4 = 83,
: }"
wondering if your goal is to block PLx overrides which I felt is something that many ODMs are using at present.
you are updating the defined power limits which is okay but why you would like to avoid any hooks to perform Plx override ?
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Change subject: mb/google/fatcat: Adjust EC host command range for fatcat_ish variant
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Patch Set 1: Code-Review+2
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Change subject: ec/acpi/ec.c: Promote timeout messages to errors
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Patch Set 1: Code-Review+1
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