coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 21 Nov '24

21 Nov '24

Uwe Poeche has posted comments on this change by Uwe Poeche. ( https://review.coreboot.org/c/coreboot/+/85177?usp=email ) Change subject: testcommit for gerrit trigger ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: start siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 21 Nov '24

21 Nov '24

Uwe Poeche has posted comments on this change by Uwe Poeche. ( https://review.coreboot.org/c/coreboot/+/85177?usp=email ) Change subject: testcommit for gerrit trigger ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: review.coreboot.org -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:44:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Shuo Liu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/lpc_gen1.c: https://review.coreboot.org/c/coreboot/+/85170/comment/900d3461_f719f5c0?us… : PS4, Line 14: register_new_ioapic_gsi0(IO_APIC_ADDR); Will ioapic0 be created with a dev object as well? (and if yes, will the register_new_ioapic_gsi0 call covered by ioapic_create_dev of ioapic 0?) -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Shuo Liu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85170/comment/3e9e1eb5_8af6a23f?us… : PS4, Line 15: from advertising wrong GSI addresses. Will the soc_get_ioapic_info and XEON_SP_HAVE_IIO_IOAPIC got totally removed in a later patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:28:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: arch/x86: Enable support for IOAPIC devices
by Shuo Liu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Lance Zhao, Patrick Rudolph, Subrata Banik, Tim Wawrzynczak, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85226?usp=email ) Change subject: arch/x86: Enable support for IOAPIC devices ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi_apic.c: https://review.coreboot.org/c/coreboot/+/85226/comment/d8f50ee5_bc56d1ea?us… : PS1, Line 243: while ((dev = dev_find_path(dev, DEVICE_PATH_IOAPIC)) != NULL) { Not sure if this part could be covered by customer MADT? CONFIG(ACPI_CUSTOM_MADT)/acpi_fill_madt? -- To view, visit https://review.coreboot.org/c/coreboot/+/85226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3 Gerrit-Change-Number: 85226 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:25:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
by Vidya Gopalakrishnan (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, V Sowmya, Vinay Kumar. Vidya Gopalakrishnan has posted comments on this change by Vidya Gopalakrishnan. ( https://review.coreboot.org/c/coreboot/+/85184?usp=email ) Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85184/comment/4388058d_0b0f8abe?us… : PS4, Line 7: Update > Decrease The PL1 values are already set elsewhere in code based on silicon ID. In this patch I am only removing the PL1 override to a higher value. Hence reworded to "Remove overriding of PL1 value to 20W". https://review.coreboot.org/c/coreboot/+/85184/comment/2485213c_43704e1c?us… : PS4, Line 9: Update the RAPL PL1 limit and MMIO PL1 max values as per silicon TDP. > Please mention the values. Done https://review.coreboot.org/c/coreboot/+/85184/comment/22868d40_97a7cd5a?us… : PS4, Line 13: Verified PL1 value is updated in DTT and sysfs interfaces. > Please paste the commands and the output. Done File src/mainboard/google/brya/variants/trulo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85184/comment/41c545fb_23942215?us… : PS4, Line 184: register "power_limits_config[ADL_N_041_6W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_7W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 25, : .tdp_pl4 = 78, : }" : : register "power_limits_config[ADL_N_081_15W_CORE]" = "{ : .tdp_pl1_override = 20, : .tdp_pl2_override = 35, : .tdp_pl4 = 83, : }" > wondering if your goal is to block PLx overrides which I felt is something that many ODMs are using […] PL1/PL2 override hooks can still be used by ODMs by adding this block of code back. But overriding PL1/PL2 to a higher value as done here should not be a default guidance given from a reference design as using a higher PLx can have thermal impacts to silicon. This code block seems to be copied from some other production device variant that is also using a higher override for PLx values. Such overrides are not part of any other reference design variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/85184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a Gerrit-Change-Number: 85184 Gerrit-PatchSet: 5 Gerrit-Owner: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:24:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Support HDMI Feature
by Subrata Banik (Code Review) 21 Nov '24

21 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85176?usp=email ) Change subject: mb/google/nissa/var/glassway: Support HDMI Feature ...................................................................... mb/google/nissa/var/glassway: Support HDMI Feature 1. Add DB_HDMI_LTE 5 on DB_USB fw_config . 2. Due to refer Nivviks, used GPP_A20/GPP_E20/GPP_E21 as default to set for NF1. Moreover, set to disable HDMI to NC when fw_config not for DB_HDMI_LTE. 3. Set related DB_USB fields to probe correct devices. BUG=b:369509276 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ic5e3b596ff3681f79f31c262e9e59d163e471e3c Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85176 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/glassway/fw_config.c M src/mainboard/google/brya/variants/glassway/gpio.c M src/mainboard/google/brya/variants/glassway/overridetree.cb M src/mainboard/google/brya/variants/glassway/variant.c 4 files changed, 46 insertions(+), 11 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c index 3cca3fe..8ed6ea6 100644 --- a/src/mainboard/google/brya/variants/glassway/fw_config.c +++ b/src/mainboard/google/brya/variants/glassway/fw_config.c @@ -5,6 +5,15 @@ #include <console/console.h> #include <fw_config.h> +static const struct pad_config hdmi_disable_pads[] = { + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), +}; + static const struct pad_config lte_disable_pads[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_NC(GPP_A8, NONE), @@ -27,8 +36,16 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n"); + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable HDMI GPIO pins.\n"); + gpio_padbased_override(padbased_table, hdmi_disable_pads, + ARRAY_SIZE(hdmi_disable_pads)); + } + + /* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE and DB_HDMI_LTE. */ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) + && !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable LTE GPIO pins.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c index f9e5c41..c2b8f70 100644 --- a/src/mainboard/google/brya/variants/glassway/gpio.c +++ b/src/mainboard/google/brya/variants/glassway/gpio.c @@ -8,8 +8,6 @@ static const struct pad_config override_gpio_table[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* A20 : DDSP_HPD2 ==> NC */ - PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D6 : WWAN_EN */ @@ -26,10 +24,6 @@ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E5 : SDD_STRAP2 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), - /* E20 : DDP2_CTRLCLK ==> NC */ - PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), - /* E21 : DDP2_CTRLDATA ==> NC */ - PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H19 : SOC_I2C_SUB_INT_ODL */ diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index b8751c7..7a12c29 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -13,6 +13,7 @@ option DB_1A 2 option DB_1C_1A 3 option DB_1C_LTE 4 + option DB_HDMI_LTE 5 end field SD_CARD 8 option SD_ABSENT 0 @@ -496,6 +497,7 @@ register "input_analog_gain" = "1" device i2c 28 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end end #I2C2 @@ -612,7 +614,12 @@ chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port use tcss_usb3_port2 as usb3_port - device generic 1 alias conn1 on end + device generic 1 alias conn1 on + probe DB_USB DB_1C + probe DB_USB DB_1A + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end end end @@ -632,7 +639,11 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end end end @@ -652,7 +663,11 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end + device ref usb2_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" @@ -667,6 +682,7 @@ register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on + probe DB_USB DB_1A probe DB_USB DB_1C_1A end end @@ -675,6 +691,7 @@ register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port4 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end chip drivers/usb/acpi @@ -709,6 +726,7 @@ register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on + probe DB_USB DB_1A probe DB_USB DB_1C_1A end end @@ -717,6 +735,7 @@ register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port2 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end end diff --git a/src/mainboard/google/brya/variants/glassway/variant.c b/src/mainboard/google/brya/variants/glassway/variant.c index 2a4d4f1..5058516 100644 --- a/src/mainboard/google/brya/variants/glassway/variant.c +++ b/src/mainboard/google/brya/variants/glassway/variant.c @@ -12,6 +12,11 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n"); + config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC; + } + if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) { printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n"); config->usb2_ports[6].enable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/85176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e3b596ff3681f79f31c262e9e59d163e471e3c Gerrit-Change-Number: 85176 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: acpi/acpigen: generate Create*Field() from name string directly
by Subrata Banik (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kyoung Il Kim, Lance Zhao, Tim Wawrzynczak. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85197?usp=email ) Change subject: acpi/acpigen: generate Create*Field() from name string directly ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/85197/comment/e1170f4d_a1caabdb?us… : PS1, Line 2441: byte word_offset ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 Gerrit-Change-Number: 85197 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:11:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for Touch controller
by Subrata Banik (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kyoung Il Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85196?usp=email ) Change subject: include/device/pci_ids.h: Add DIDs for Touch controller ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: should be clubbed with CB:85198 -- To view, visit https://review.coreboot.org/c/coreboot/+/85196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9acd9dbba1cca1bb90bf49dbc3a1882262bd474 Gerrit-Change-Number: 85196 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update Touch Controller UPD params
by Subrata Banik (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) Change subject: soc/intel/pantherlake: Update Touch Controller UPD params ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85199/comment/7acdee00_a4879f8b?us… : PS1, Line 565: > good point. Let me use the same conditions as thcAssignment. Acknowledged File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85199/comment/522c7b03_20a3de76?us… : PS2, Line 564: ThcAssignment What are the default values of these UPDs? If not, then we may want to set them to zero when THC0/1 are not enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 10:09:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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