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Change subject: mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD
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Patch Set 1: Code-Review+2
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Change subject: mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD
......................................................................
mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD
This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at the 16MB boundary.
Additionally, fix typo in flash descriptor comment, where comment
incorrectly referred to "MTL" instead of "PTL".
TEST=Successfully builds google/fatcat.
Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84899/1
diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
index f34e495..8d41977 100644
--- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
@@ -9,6 +9,15 @@
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
+ # This section starts at the 16M boundary in SPI flash.
+ # PTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7680K {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ }
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
@@ -22,15 +31,6 @@
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
- # This section starts at the 16M boundary in SPI flash.
- # MTL does not support a region crossing this boundary,
- # because the SPI flash is memory-mapped into two non-
- # contiguous windows.
- RW_SECTION_B 7680K {
- VBLOCK_B 8K
- FW_MAIN_B(CBFS)
- RW_FWID_B 64
- }
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor
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Change subject: mb/google/nissa/var/teliks: Match VBT with SSFC
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Patch Set 12:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84871/comment/634f25a3_4b7dfd50?us… :
PS7, Line 10: SSFC
> SSFC is a type of CBI.
The commit message still misses, why SSFC is the way for distinguishing them, and not some other feature like fw_config.
https://review.coreboot.org/c/coreboot/+/84871/comment/cd7702ef_df1d9232?us… :
PS7, Line 12:
> Yes, I have set up two VBTs locally. Let the two VBTs match the 11.6 panel and 12. […]
But you verify them in your change, don’t you. Don’t they need to be added?
https://review.coreboot.org/c/coreboot/+/84871/comment/d5eb8ae2_af01f29f?us… :
PS7, Line 14: can match VBT with SSFC
> After the system starts, we can query the log printed in mainboard_vbt_filename by entering: "cat /s […]
Please add that to the commit message, and maybe even add your logs.
https://review.coreboot.org/c/coreboot/+/84871/comment/6d30161c_24d27f14?us… :
PS7, Line 15: can pass platform_BootPerf test
> This test needs to be entered in the chroot environment: "test_that -b {BOARD_NAME} {device IP} plat […]
Please add that.
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Change subject: soc/amd/common/psp: add code for reporting RPMC status
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Patch Set 5: Code-Review+1
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Change subject: tree: Fix cast an object of type 'nullptr_t' to 'uintptr_t' error
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Patch Set 2:
(1 comment)
File tests/lib/imd-test.c:
https://review.coreboot.org/c/coreboot/+/84893/comment/f0c16651_b4add74f?us… :
PS1, Line 235: (uintptr_t)(void *)0;
> Can these be just `0`?
Done
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