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Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75137/comment/06eba550_ef6d701e?us… :
PS6, Line 9: Per Fabian:
:
: With these settings enabled COM 1/UART A/serial port 1 gets blocked
: right after the kernel boots. It no longer works or responds, which
: actually means the Linux boot process gets stuck forever when configured
: to write to ttyS0.
:
: Not using these settings, I have not found any downside. Serial keeps
: working, sensors still work, S3 suspend/resume works correctly.
:
: ---
:
: Out of the six settings in this group, three are causing the initial
: issue, the rest are confirmed necessary to be replicated, with PECI
: as the reason for one of them. Keith revised this patch to reflect
: this.
> I’d prefer one coherent message. […]
In short, the first 3 global settings (0x26, 0x13, 0x14) that Fabian tried to revert are causing his troubles, and I agree with him that those should go. The remaining global settings I replicated from vendor FW are necessary and have to remain.
I would love a suggestion on how to improve the messaging, without appearing as if I completely appropriated Fabian's work, as he deserves at least some credit.
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Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75137/comment/fdf5828d_4aafff1e?us… :
PS6, Line 9: Per Fabian:
:
: With these settings enabled COM 1/UART A/serial port 1 gets blocked
: right after the kernel boots. It no longer works or responds, which
: actually means the Linux boot process gets stuck forever when configured
: to write to ttyS0.
:
: Not using these settings, I have not found any downside. Serial keeps
: working, sensors still work, S3 suspend/resume works correctly.
:
: ---
:
: Out of the six settings in this group, three are causing the initial
: issue, the rest are confirmed necessary to be replicated, with PECI
: as the reason for one of them. Keith revised this patch to reflect
: this.
I’d prefer one coherent message. But I’d also be content with a clear statement in the commit message, what is now replicated the vendor firmware, and what is not.
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Change subject: Documentation: Add information about the deguard utility
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84825/comment/77fcc47e_e407a222?us… :
PS2, Line 10:
The Signed-off-by line is missing.
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Change subject: soc/intel/pantherlake: Update SAF base address
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/84863/comment/76092b76_8d60c83b?us… :
PS2, Line 19: SAF_BASE_ADDRESS
what is the source here ? please let me know for my verification
FAS says
```Same BAR as on LNL and it is programmed by BIOS.```
Take a look into 6.2 section of the same doc `P2SB BARs and SAFBAR will be
moved to above 4GB`
SAF BAR - 0x3F_FE00_0000 to 0x3F_FFFF_FFFF
Size - 32MB
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Change subject: mb/system76: Enable S0ix support but prefer S3
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Change subject: soc/intel: Add config to use S3 over S0ix
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 28:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/1d5730c6_7a9cc611?us… :
PS28, Line 242: gpe0_mask
> it is intended to use gpe0_mask as the argument. Please the the comment on line 239-240.
Done
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/fd4a3db1_751b958c?us… :
PS28, Line 522: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
> no. gpe1_sts and gpe1_en are only defined in the structure also based on the same config flag.
Done
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Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84888/comment/eec776c1_7bf251a6?us… :
PS2, Line 618: AUDIO_MAX98360_ALC5682I_I2S
> thsi is already taken care in fw_config changes that is merged.
Acknowledged
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Change subject: soc/intel/pantherlake: Update SAF base address
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Set Ready For Review
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Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec
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Patch Set 2:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84888/comment/91f4032e_d22cb527?us… :
PS2, Line 618: AUDIO_MAX98360_ALC5682I_I2S
> do we need to perform any GPIO programming for programming into i2s mode or already taken care ?
thsi is already taken care in fw_config changes that is merged.
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