coreboot-gerrit October 2024

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[L] Change in coreboot[main]: Add UPL FDT handoff
by Benjamin Doron (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Jakub Czapiga, Julius Werner, Jérémy Compostella, Matt DeVillier, Maximilian Brune, Philipp Hug, Simon Glass, ron minnich. Benjamin Doron has uploaded a new patch set (#24) to the change originally created by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/76591?usp=email ) Change subject: Add UPL FDT handoff ...................................................................... Add UPL FDT handoff This adds another handoff that is basically the same as coreboot tables. The only real difference is that it uses the devicetree format to transfer the information to payload. This handoff is inspired by the UPL (universal payload) specification. Tested: start q35 qemu with coreinfo as payload and see that console still works and the devicetree is printed by coreboot. Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M payloads/Kconfig M src/arch/arm/include/arch/cbconfig.h M src/arch/arm64/include/arch/cbconfig.h M src/arch/ppc64/include/arch/cbconfig.h M src/arch/riscv/include/arch/cbconfig.h M src/arch/x86/include/arch/cbconfig.h M src/arch/x86/tables.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/boot/coreboot_tables.h M src/include/boot/tables.h A src/include/boot/upl_fdt_table.h M src/lib/Makefile.mk M src/lib/bootmem.c M src/lib/coreboot_table.c A src/lib/tables.c A src/lib/upl_fdt_table.c M tests/lib/Makefile.mk 20 files changed, 437 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/76591/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/76591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Gerrit-Change-Number: 76591 Gerrit-PatchSet: 24 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

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[L] Change in coreboot[main]: payloads/libpayload: Implement support for UPL handoff
by Benjamin Doron (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Maximilian Brune. Hello Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84797?usp=email to look at the new patch set (#2). Change subject: payloads/libpayload: Implement support for UPL handoff ...................................................................... payloads/libpayload: Implement support for UPL handoff Change-Id: I0caa0cf5ef432c7e4b898931a8a0bd6c72b1e665 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/arch/arm/coreboot.c M payloads/libpayload/arch/arm64/coreboot.c M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/Makefile.mk A payloads/libpayload/libc/upl_fdt.c 7 files changed, 268 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84797/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84797?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0caa0cf5ef432c7e4b898931a8a0bd6c72b1e665 Gerrit-Change-Number: 84797 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS
by Subrata Banik (Code Review) 28 Oct '24

28 Oct '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84903?usp=email ) Change subject: soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS ...................................................................... soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS This patch implements the `save_dimm_info()` API to populate and pass DRAM-related information to the next stage. This information is used to generate the SMBIOS memory table, providing details about installed DIMMs. This addresses the issue where SMBIOS lacked detailed DIMM information. Verified that `dmidecode` correctly dumps the DIMM information from the SMBIOS table after this change. BUG=b:376103463 TEST=Built and booted successfully. Verified DIMM info in SMBIOS using `dmidecode`. > dmidecode -t 17 ``` Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ... ... Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-3-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-3-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ``` Change-Id: I3b942610272de401589ee0463de9cd0985974774 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/romstage/romstage.c 1 file changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84903/1 diff --git a/src/soc/intel/pantherlake/romstage/romstage.c b/src/soc/intel/pantherlake/romstage/romstage.c index a05adc4..46be7b9 100644 --- a/src/soc/intel/pantherlake/romstage/romstage.c +++ b/src/soc/intel/pantherlake/romstage/romstage.c @@ -18,10 +18,107 @@ #include <string.h> #include <timestamp.h> +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { - /* Update after FSP is released externally released. */ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len = 0; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (!meminfo_hob || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (!mem_info) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) + dram_part_num_len = strlen(dram_part_num); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!dram_part_num) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + uint8_t memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType, + node, + meminfo_hob->MaximumMemoryClockSpeed); + index++; + } + } + } + mem_info->dimm_cnt = index; + if (mem_info->dimm_cnt == 0) + printk(BIOS_ERR, "No DIMMs found\n"); + else + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } void mainboard_romstage_entry(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/84903?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b942610272de401589ee0463de9cd0985974774 Gerrit-Change-Number: 84903 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Paul Menzel (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui. Paul Menzel has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75137/comment/61cb6fe2_1c350f71?us… : PS6, Line 9: Per Fabian: : : With these settings enabled COM 1/UART A/serial port 1 gets blocked : right after the kernel boots. It no longer works or responds, which : actually means the Linux boot process gets stuck forever when configured : to write to ttyS0. : : Not using these settings, I have not found any downside. Serial keeps : working, sensors still work, S3 suspend/resume works correctly. : : --- : : Out of the six settings in this group, three are causing the initial : issue, the rest are confirmed necessary to be replicated, with PECI : as the reason for one of them. Keith revised this patch to reflect : this. > Settings at issue concerns IRQ polarity. The 0x26 is to unlock them. […] Understood. If you think the current state is the good, then feel free to mark the comment as resolved. -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 6 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Mon, 28 Oct 2024 20:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Keith Hui (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Fabian Groffen, Keith Hui, Paul Menzel. Keith Hui has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75137/comment/f28974b8_6ce23830?us… : PS6, Line 9: Per Fabian: : : With these settings enabled COM 1/UART A/serial port 1 gets blocked : right after the kernel boots. It no longer works or responds, which : actually means the Linux boot process gets stuck forever when configured : to write to ttyS0. : : Not using these settings, I have not found any downside. Serial keeps : working, sensors still work, S3 suspend/resume works correctly. : : --- : : Out of the six settings in this group, three are causing the initial : issue, the rest are confirmed necessary to be replicated, with PECI : as the reason for one of them. Keith revised this patch to reflect : this. > What are the defaults, after the settings are removed? […] Settings at issue concerns IRQ polarity. The 0x26 is to unlock them. Power on defaults to all high; vendor have them as all low, but we all came to agree that power on defaults should not be altered. Fabian is reverting six settings. I found that only the first 3 reverts (IRQ polarity above) are warranted and the rest have to stay. It was also me that updated this patch, because I tried to contact him and have him do it but couldn't reach him. -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 6 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Mon, 28 Oct 2024 20:03:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: ec/dasharo/ec: add Dasharo features
by Paul Menzel (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Felix Singer, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Paul Menzel has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82672?usp=email ) Change subject: ec/dasharo/ec: add Dasharo features ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82672/comment/00d6ffa1_2dc4a323?us… : PS12, Line 13: > Sadly there is no way currently Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/82672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Gerrit-Change-Number: 82672 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Mon, 28 Oct 2024 19:40:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Paul Menzel (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui. Paul Menzel has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75137/comment/f80b9f6e_a96d7902?us… : PS6, Line 7: Remove settings to replicate OEM Remove 3 global settings to fix serial port 1 https://review.coreboot.org/c/coreboot/+/75137/comment/a1c8f7c9_a2d68d68?us… : PS6, Line 9: Per Fabian: : : With these settings enabled COM 1/UART A/serial port 1 gets blocked : right after the kernel boots. It no longer works or responds, which : actually means the Linux boot process gets stuck forever when configured : to write to ttyS0. : : Not using these settings, I have not found any downside. Serial keeps : working, sensors still work, S3 suspend/resume works correctly. : : --- : : Out of the six settings in this group, three are causing the initial : issue, the rest are confirmed necessary to be replicated, with PECI : as the reason for one of them. Keith revised this patch to reflect : this. > In short, the first 3 global settings (0x26, 0x13, 0x14) that Fabian tried to revert are causing his […] What are the defaults, after the settings are removed? In my opinion Fabian’s Signed-off-by give credit. But a separate sentence saying, that Fabian did a lot of debugging work and found six settings would also be warranted. -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 6 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Mon, 28 Oct 2024 19:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration
by Cliff Huang (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email ) Change subject: soc/intel/common/gpio: add function to lock GPIO configuration ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabe4e4b1d282a5f6cae8f330100c9139e0c2691d Gerrit-Change-Number: 84901 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 28 Oct 2024 19:34:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat: Apply GPIO configuration lock
by Cliff Huang (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84902?usp=email ) Change subject: mb/google/fatcat: Apply GPIO configuration lock ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc991910b9d3f2dae4b1a07bcf16ad7ac4bc61ca Gerrit-Change-Number: 84902 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 28 Oct 2024 19:34:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants
by Subrata Banik (Code Review) 28 Oct '24

28 Oct '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84900?usp=email ) Change subject: mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants ...................................................................... mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for different Fatcat variants. The EC_SYNC_IRQ macro is used for tight timestamps and wake support, while the GPIO_PCH_WP macro is used for the WP signal to the PCH. These macros were previously undefined or incorrectly defined for some variants. This commit fixes these issues and ensures that the macros are defined correctly for all variants. Specifically, this commit: - Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE. - Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat. - Defines GPIO_PCH_WP as GPP_D02 for Fatcat. - Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka. TEST=Able to build and boot google/fatcat. w/o this patch: ``` cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22) cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22 ``` w/ this patch: ``` cros_ec_lpcs GOOG0004:00: Chrome EC device registered ``` Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h 2 files changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84900/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h index b9b4689..c354e8b 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h @@ -75,8 +75,10 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ -#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ +#if !CONFIG(BOARD_GOOGLE_FATCAT) + #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ + #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ +#endif #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index 5a77e4e..3f94c03 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -6,12 +6,21 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* FIXME: update below code as per board schematics */ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -/* GPIO IRQ for tight timestamps / wake support */ -#define EC_SYNC_IRQ 0 -/* WP signal to PCH */ -#define GPIO_PCH_WP 0 +/* + * EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support + * GPIO_PCH_WP - WP signal to PCH + */ +#if CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATITE) + #define EC_SYNC_IRQ GPP_E07_IRQ + #define GPIO_PCH_WP GPP_D02 +#elif CONFIG(BOARD_GOOGLE_FATCAT) + #define EC_SYNC_IRQ 0 /* Not Connected */ + #define GPIO_PCH_WP GPP_D02 +#elif CONFIG(BOARD_GOOGLE_FRANCKA) + #define EC_SYNC_IRQ 0 /* TODO */ + #define GPIO_PCH_WP 0 /* TODO */ +#endif #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7 Gerrit-Change-Number: 84900 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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