coreboot-gerrit October 2024

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Adjust touchpad I2C frequency to less t...
by Weimin Wu (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: hualin wei. Weimin Wu has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/84898?usp=email ) Change subject: mb/google/dedede/var/awasuki: Adjust touchpad I2C frequency to less than 400 KHz ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Gerrit-Change-Number: 84898 Gerrit-PatchSet: 1 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 01:14:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Adjust touchpad I2C frequency to less t...
by hualin wei (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Weimin Wu. hualin wei has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/84898?usp=email ) Change subject: mb/google/dedede/var/awasuki: Adjust touchpad I2C frequency to less than 400 KHz ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/84898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Gerrit-Change-Number: 84898 Gerrit-PatchSet: 1 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 01:13:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update SAF base address
by Anil Kumar K (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Anil Kumar K has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/84863?usp=email ) Change subject: soc/intel/pantherlake: Update SAF base address ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84863/comment/1c1ce866_1bf1f8ea?us… : PS2, Line 19: SAF_BASE_ADDRESS > what is the source here ? please let me know for my verification […] I will check and confirm Subrata.. our internal doc says 0xfa000000 which is not reflected in public doc. -- To view, visit https://review.coreboot.org/c/coreboot/+/84863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Gerrit-Change-Number: 84863 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 29 Oct 2024 00:37:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Yu-Ping Wu (Code Review) 29 Oct '24

29 Oct '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8196/include/soc/irq2axi.h: https://review.coreboot.org/c/coreboot/+/84896/comment/7d76654d_47bec09f?us… : PS1, Line 14: irq2axi_uninit > just rename it to `disable_irq2axi` Or `irq2axi_disable`? -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 28 Oct 2024 23:45:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: uncore_acpi: Clean up resource code
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84829?usp=email ) Change subject: uncore_acpi: Clean up resource code ...................................................................... uncore_acpi: Clean up resource code Use the resource size to determine Vtd BAR size and drop the code to calculate the Vtd BAR size. While on it do not truncate the resource address to 32-bit, since the DMAR entry is 64-bit wide anyway. TEST: Booted on intel/archercity_crb Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 7 insertions(+), 11 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index fc283ee..099b235 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -251,11 +251,7 @@ struct resource *resource; resource = probe_resource(iommu, VTD_BAR_CSR); - if (!resource) - return current; - - uint32_t reg_base = resource->base; - if (!reg_base) + if (!resource || !resource->base || !resource->size) return current; const uint32_t bus = iommu->upstream->secondary; @@ -263,8 +259,8 @@ int socket = iio_pci_domain_socket_from_dev(iommu); int stack = iio_pci_domain_stack_from_dev(iommu); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%llx\n", + __func__, socket, stack, bus, pcie_seg, resource->base); /* * Add DRHD Hardware Unit @@ -276,10 +272,10 @@ DRHD_INCLUDE_PCI_ALL : 0; printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - flags, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, flags, - pcie_seg, reg_base, vtd_probe_bar_size(iommu)); + "Register Base Address: 0x%llx\n", + flags, pcie_seg, resource->base); + current += acpi_create_dmar_drhd(current, flags, pcie_seg, resource->base, + resource->size); // Add IOAPIC if (is_dev_on_domain0(iommu)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/84829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5 Gerrit-Change-Number: 84829 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Fix iiostack.asl
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84795?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Fix iiostack.asl ...................................................................... soc/intel/xeon_sp: Fix iiostack.asl Align DSDT names with SSDT naming scheme, as provided by iio_domain_set_acpi_name() and hide unused devices by implementing the _STA method as done on newer platforms. Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84795 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl 1 file changed, 16 insertions(+), 4 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl index 0dd39a0..53e144a 100644 --- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl @@ -6,6 +6,17 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ Name (_UID, 0x##id) \ + Method (_STA, 0, NotSerialized) \ + { \ + If (CondRefOf (_CRS)) \ + { \ + Return (0xf) \ + } \ + Else \ + { \ + Return (0) \ + } \ + } \ Method (_PRT, 0, NotSerialized) \ { \ If (PICM) \ @@ -60,14 +71,15 @@ } \ } +// Keep in sync with iio_domain_set_acpi_name()! MAKE_IIO_DEV(00, 00) MAKE_IIO_DEV(01, 10) MAKE_IIO_DEV(02, 20) MAKE_IIO_DEV(03, 28) #if (CONFIG_MAX_SOCKET > 1) -MAKE_IIO_DEV(06, 40) -MAKE_IIO_DEV(07, 50) -MAKE_IIO_DEV(08, 60) -MAKE_IIO_DEV(09, 68) +MAKE_IIO_DEV(20, 40) +MAKE_IIO_DEV(21, 50) +MAKE_IIO_DEV(22, 60) +MAKE_IIO_DEV(23, 68) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb Gerrit-Change-Number: 84795 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add SAD PCI driver
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84794?usp=email ) Change subject: soc/intel/xeon_sp: Add SAD PCI driver ...................................................................... soc/intel/xeon_sp: Add SAD PCI driver Get rid of some helper functions by properly using a pci_driver. Configure SAD if necessary and lock SAD if necessary in the newly added SAD PCI driver. This allows to drop lock_pam0123(), unlock_pam_regions() and socket0_get_ubox_busno(). - Fixes SAD instance on secondary sockets not decoding the C-F segments as DRAM, which would prevent those sockets to access the ACPI/SMBIOS table anchor - Adds PCI multi segment support (SKX and CPX only, other were working properly already) - Moves locking of PAM0123_CSR and PAM456_CSR from SoC to driver code Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84794 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/finalize.c M src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h A src/soc/intel/xeon_sp/sad.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 17 files changed, 72 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 1f68f27..0fc32d8 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -21,6 +21,8 @@ ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c +ramstage-y += sad.c + smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index ee167e2..9737d11 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -181,28 +181,3 @@ else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(sr)) create_ioat_domains(dp, bus, sr, pci_segment_group); } - -/* - * Route PAM segment access to DRAM - * Only call this code from socket0! - */ -void unlock_pam_regions(void) -{ - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - /* Get UBOX(1) for socket0 */ - uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); - - /* Assume socket0 owns PCI segment 0 */ - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index e6b2bdb..afa5357 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -163,8 +163,6 @@ static void chip_init(void *data) { - unlock_pam_regions(); - printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 60b2a82..a92d9d0 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -34,7 +34,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); -uint8_t socket0_get_ubox_busno(const uint8_t stack); uint8_t get_cxl_node_count(void); int soc_get_stack_for_port(int port); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index aac5589..cc872c0 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -35,18 +35,6 @@ return res->Personality == TYPE_UBOX; } -/* Returns the UBOX(stack) bus number when called from socket0 */ -uint8_t socket0_get_ubox_busno(const uint8_t stack) -{ - if (stack >= MAX_IIO_STACK) { - printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); - return 0; - } - const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); - const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; - return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; -} - /* * EX: CPX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index fa39eb6..a7b36027 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -60,7 +60,6 @@ setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); apm_control(APM_CNT_FINALIZE); - lock_pam0123(); if (CONFIG_MAX_SOCKET > 1) { /* This MSR is package scope but run for all cpus for code simplicity */ diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h index e2c63db..fab090a 100644 --- a/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h @@ -37,6 +37,7 @@ #define SAD_ALL_DEV CHA_DEV #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x80 +#define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x84 #define SAD_ALL_DEVID 0x344f diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index ed278a3..73eeea5 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -85,8 +85,6 @@ #define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) -void unlock_pam_regions(void); - size_t vtd_probe_bar_size(struct device *dev); void soc_pci_domain_fill_ssdt(const struct device *domain); diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index a7b98f3..4c7c75f 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -9,8 +9,6 @@ #define MEM_ADDR_64MB_SHIFT_BITS 26 -void lock_pam0123(void); - msr_t read_msr_ppin(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); diff --git a/src/soc/intel/xeon_sp/sad.c b/src/soc/intel/xeon_sp/sad.c new file mode 100644 index 0000000..78545f5 --- /dev/null +++ b/src/soc/intel/xeon_sp/sad.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/cfg.h> +#include <intelpch/lockdown.h> +#include <soc/pci_devs.h> + +/* + * Driver for SAD device (SKX and CPX only), now called CHA dev. + * SKX/CPX [B(31), D:29, F:0/F:1] + * SPR/GNR [B(31), D:29, F:0/F:1] + */ + +static void sad_enable_resources(struct device *dev) +{ + pci_dev_enable_resources(dev); + + if (!CONFIG(SOC_INTEL_SKYLAKE_SP) && !CONFIG(SOC_INTEL_COOPERLAKE_SP)) + return; + + /* + * Enables the C-F segment as DRAM. Only necessary on SKX and CPX, that do + * not unconditionally enable those segments in FSP. + * The assumption here is that FSP-S does not need to access the C-F segment, + * and nothing in coreboot should access those segments before writing tables. + */ + + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + pci_write_config32(dev, SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_write_config32(dev, SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_read_config32(dev, SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_read_config32(dev, SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +static void sad_final(struct device *dev) +{ + if (!CONFIG(SOC_INTEL_COMMON_PCH_LOCKDOWN)) + return; + + if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) + return; + + pci_or_config32(dev, SAD_ALL_PAM0123_CSR, PAM_LOCK); +} + +static const unsigned short sad_ids[] = { + SAD_ALL_DEVID, + 0 +}; + +static struct device_operations sad_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = sad_enable_resources, + .final = sad_final, +}; + +static const struct pci_driver sad_driver __pci_driver = { + .ops = &sad_ops, + .vendor = PCI_VID_INTEL, + .devices = sad_ids, +}; diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 37535a3..653f2b1 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -38,8 +38,6 @@ static void soc_init(void *data) { - unlock_pam_regions(); - printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index b8c000e..4345e46 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -13,8 +13,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); -uint8_t socket0_get_ubox_busno(const uint8_t stack); - int soc_get_stack_for_port(int port); uint8_t get_cxl_node_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 0938260..9d68d44 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -83,18 +83,6 @@ return false; } -/* Returns the UBOX(stack) bus number when called from socket0 */ -uint8_t socket0_get_ubox_busno(const uint8_t stack) -{ - if (stack >= MAX_IIO_STACK) { - printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); - return 0; - } - const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); - const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; - return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; -} - #if ENV_RAMSTAGE void config_reset_cpl3_csrs(void) { diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 510a67f..ae1a020 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -22,6 +22,7 @@ #define SAD_ALL_DEV CHA_DEV #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x80 +#define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x84 #define SAD_ALL_DEVID 0x344f diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index 463e619..df498e9 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -44,7 +44,6 @@ const EWL_PRIVATE_DATA *get_ewl_hob(void); -uint8_t socket0_get_ubox_busno(uint8_t offset); void soc_set_mrc_cold_boot_flag(bool cold_boot_required); void soc_config_iio(FSPM_UPD *mupd, const UPD_IIO_PCIE_PORT_CONFIG_ENTRY mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS], const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5]); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 6dd06ac..a6f00c0 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -136,20 +136,6 @@ return count; } -/* Returns the UBOX(offset) bus number for socket0 */ -uint8_t socket0_get_ubox_busno(uint8_t offset) -{ - const IIO_UDS *hob = get_iio_uds(); - - for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { - if (hob->PlatformData.IIO_resource[0].StackRes[stack].Personality - == TYPE_UBOX) - return (hob->PlatformData.IIO_resource[0].StackRes[stack].BusBase - + offset); - } - die("Unable to locate UBOX BUS NO"); -} - void bios_done_msr(void *unused) { msr_t msr = rdmsr(MSR_BIOS_DONE); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index bf07ee7..69f3c15 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -123,20 +123,6 @@ #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ -void lock_pam0123(void) -{ - const uint32_t pam0123_lock = 0x33333331; - struct device *dev; - - if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) - return; - - dev = NULL; - /* Look for SAD_ALL devices on all sockets */ - while ((dev = dev_find_device(PCI_VID_INTEL, SAD_ALL_DEVID, dev))) - pci_write_config32(dev, SAD_ALL_PAM0123_CSR, pam0123_lock); -} - /* return true if command timed out else false */ static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask, uint32_t target) -- To view, visit https://review.coreboot.org/c/coreboot/+/84794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1 Gerrit-Change-Number: 84794 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: lib/smbios: Improve Type9
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78292?usp=email ) Change subject: lib/smbios: Improve Type9 ...................................................................... lib/smbios: Improve Type9 Set characteristics 1 based on slot type and scan PCI capabilities to update the characteristics 2 field in SMBIOS type 9 accordingly. Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78292 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/lib/smbios.c 1 file changed, 21 insertions(+), 4 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Benjamin Doron: Looks good to me, approved diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 58caf8c..9cee637 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <version.h> #include <device/device.h> +#include <device/pciexp.h> #include <device/dram/spd.h> #include <elog.h> #include <endian.h> @@ -1136,6 +1137,7 @@ enum slot_data_bus_bandwidth bandwidth; enum misc_slot_type type; enum misc_slot_length length; + uint8_t characteristics_1 = 0, characteristics_2 = 0; if (dev->path.type != DEVICE_PATH_PCI) return 0; @@ -1156,16 +1158,31 @@ else bandwidth = SlotDataBusWidthUnknown; - if (dev->smbios_slot_type) + if (dev->smbios_slot_type > SlotTypeUnknown) { type = dev->smbios_slot_type; - else + if ((type >= SlotTypePciExpress && type <= SlotTypeEDSFF_E3) || + (type >= SlotTypeAgp && type <= SlotTypeM2Socket3) || + (type == SlotTypePci)) { + characteristics_1 |= SMBIOS_SLOT_3P3V; + } + if ((type >= SlotTypeAgp && type <= SlotTypeAgp8X) || + (type == SlotTypePci)) + characteristics_1 |= SMBIOS_SLOT_5V; + } else { + characteristics_1 = SMBIOS_SLOT_UNKNOWN; type = SlotTypeUnknown; + } if (dev->smbios_slot_length) length = dev->smbios_slot_length; else length = SlotLengthUnknown; + if (pci_has_pme_pin(dev)) + characteristics_2 |= SMBIOS_SLOT_PME; + if (CONFIG(PCIEXP_PLUGIN_SUPPORT) && pciexp_dev_is_slot_hot_plug_cap(dev)) + characteristics_2 |= SMBIOS_SLOT_HOTPLUG; + return smbios_write_type9(current, handle, dev->smbios_slot_designation, type, @@ -1173,8 +1190,8 @@ usage, length, 0, - 1, - 0, + characteristics_1, + characteristics_2, dev->upstream->segment_group, dev->upstream->secondary, dev->path.pci.devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/78292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Gerrit-Change-Number: 78292 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: pci: Add method to read PME capability
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84793?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: pci: Add method to read PME capability ...................................................................... pci: Add method to read PME capability Add a helper method to read the PME capability. Will be used in the following commit. Change-Id: Id1fdc98c9ce86d3ddf8056bb609afc58008cf2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84793 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/device/pci_device.c M src/include/device/pci.h 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Shuo Liu: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a2ad2b3..d03d88d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1346,6 +1346,24 @@ } /** + * Returns if the device support PMEs. + * + * @param dev Pointer to the device structure. + * @return Returns true when the device support PMEs. The PME generation can be + * disabled though. + */ +bool pci_has_pme_pin(const struct device *dev) +{ + const uint16_t cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!cap) + return false; + + const uint16_t pmecap = pci_read_config16(dev, cap + PCI_PM_PMC); + + return !!(pmecap & PCI_PM_CAP_PME); +} + +/** * PCI devices that are marked as "hidden" do not get probed. However, the same * initialization logic is still performed as if it were. This is useful when * devices would like to be described in the devicetree.cb file, and/or present diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 2e75195..83d6628 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -98,6 +98,7 @@ void pci_dev_init(struct device *dev); unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); uint16_t pci_find_cap_recursive(const struct device *dev, uint16_t cap); +bool pci_has_pme_pin(const struct device *dev); const char *pin_to_str(int pin); int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); -- To view, visit https://review.coreboot.org/c/coreboot/+/84793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1fdc98c9ce86d3ddf8056bb609afc58008cf2e9 Gerrit-Change-Number: 84793 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: lib/smbios: Improve Type9
by Lean Sheng Tan (Code Review) 28 Oct '24

28 Oct '24

Attention is currently required from: Angel Pons, Kyösti Mälkki, Maximilian Brune, Patrick Rudolph, Paul Menzel. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/78292?usp=email ) Change subject: lib/smbios: Improve Type9 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78292/comment/f1245a07_0b0665c4?us… : PS3, Line 7: Improve Type9 : > Something more specific would be nice. Feel free to ignore, if not possible. thought of it and briefly discussed with Ben, doesn’t seems to be relevant - will ack it and get it merged. thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/78292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Gerrit-Change-Number: 78292 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 28 Oct 2024 22:05:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit October 2024