coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Jérémy Compostella (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik. Hello Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84552?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... soc/intel/pantherlake: Add FSP-S programming FSP-S UPDs are programmed according to the configuration (Kconfig and device tree) in ramstage. BUG=348678529 TEST=Hardware is programmed as desired and Intel Panther Lake reference board boots to UI. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/fsp_params.c 1 file changed, 734 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84552/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 14 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add GPIO settings
by Cliff Huang (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Jérémy Compostella, Pranava Y N, Subrata Banik, Wonkyu Kim. Cliff Huang has uploaded a new patch set (#22) to the change originally created by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email ) Change subject: mb/google/fatcat: Add GPIO settings ...................................................................... mb/google/fatcat: Add GPIO settings BUG=b:348678529 TEST=Boot google fatcat board till FSP memory training Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h 3 files changed, 417 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84405/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/84405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Gerrit-Change-Number: 84405 Gerrit-PatchSet: 22 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSI
by 9elements QA (Code Review) 01 Oct '24

01 Oct '24

9elements QA has posted comments on this change by Jameson Thies. ( https://review.coreboot.org/c/coreboot/+/84404?usp=email ) Change subject: chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSI ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/220995 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/220993 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/220992 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/220991 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/220990 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/220989 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/220988 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/220987 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/220986 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/220985 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/220984 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/220983 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/84404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652 Gerrit-Change-Number: 84404 Gerrit-PatchSet: 7 Gerrit-Owner: Jameson Thies <jthies(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Abhishek Pandit-Subedi <abhishekpandit(a)google.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 18:07:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Jérémy Compostella (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/bdddf1b3_1e54732c?us… : PS11, Line 250: static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, : const struct soc_intel_pantherlake_config *config) : { : const struct microcode *microcode; : size_t length; : : if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) : s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); : : if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) { : /* Locate microcode and pass to FSP-S for 2nd microcode loading */ : microcode = intel_microcode_find(); : if (!microcode) : return; : : length = get_microcode_size(microcode); : if (!length) : return; : : /* Update CPU Microcode patch base address/size */ : s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode; : s_cfg->MicrocodeRegionSize = (uint32_t)length; : } : } > 1. USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI <— FSP runs coreboot APIs > 2. USE_INTEL_FSP_MP_INIT <— FSP runs own APIs > > in case #2 , filling the CpuMpPpi UPD won't harm. That is simply not true. If `CpuMpPpi` is set while `USE_INTEL_FSP_MP_INIT=y` and `CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI=n` the FSP hit some exceptions inside coreboot MP functions because some initialization were not performed. If Is set to `NULL` which clearly is what is appropriate under this configuration when the CPU initialization execute just fine. > if you wish to use #2 (which we don't plan to use) then please select USE_INTEL_FSP_MP_INIT config. I do not plan on changing the default configuration, this is just about setting the UPD appropriately. -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 17:36:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet
by Marshall Dawson (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune, Paul Menzel. Marshall Dawson has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/.../amd_pci_int_defs.h: Update according to datasheet ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84574/comment/fa76c96a_44caafdc?us… : PS4, Line 9: MISC2/3 1/2 or is my math wrong? Otherwise the patch LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Oct 2024 17:30:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/amd/birman_plus/devicetree_glinda.cb: Update USB
by Marshall Dawson (Code Review) 01 Oct '24

01 Oct '24

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[M] Change in coreboot[main]: mb/amd/birman_plus/devicetree_glinda.cb: Update USB
by Marshall Dawson (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Maximilian Brune. Marshall Dawson has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84436?usp=email ) Change subject: mb/amd/birman_plus/devicetree_glinda.cb: Update USB ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84436/comment/0407f28d_c1fc48fc?us… : PS4, Line 9: Signed-off-by: Satya SreenivasL <satya.sreenivasl(a)amd.com> : Change-Id: I0603f5da689b6738ea54305a665b150121bc520c : Reviewed-by: Anand Vaikar <a.vaikar2021(a)gmail.com> : Reviewed-by: Ritul Guru <ritul.bits(a)gmail.com> : Tested-by: Satya Sreenivas L <Satya.SreenivasL(a)amd.com> : Consider prepending these with "Original-" to keep the git history clean? File src/mainboard/amd/birman_plus/devicetree_glinda.cb: https://review.coreboot.org/c/coreboot/+/84436/comment/9f695441_336c750d?us… : PS4, Line 140: .txvreftune = 0x6, 3? I'm comparing against AmdCpmPkg/Addendum/Oem/BirmanPlus/AmdCpmPkg.inc.dsc https://review.coreboot.org/c/coreboot/+/84436/comment/3a81a6ed_8abb2035?us… : PS4, Line 154: .txvreftune = 0x6 3? -- To view, visit https://review.coreboot.org/c/coreboot/+/84436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacf9ab43c337a8b6a7aa5a37eb8a59644fcaeac6 Gerrit-Change-Number: 84436 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 17:01:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/fatcat: Add GPIO settings
by Cliff Huang (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Jérémy Compostella, Pranava Y N, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email ) Change subject: mb/google/fatcat: Add GPIO settings ...................................................................... Patch Set 21: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/gpio.c: https://review.coreboot.org/c/coreboot/+/84405/comment/a5245949_232a3e86?us… : PS21, Line 412: /* GPP_C00: GPP_C0_SMBCLK */ : PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), : /* GPP_C01: GPP_C1_SMBDATA */ : PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), : > should this move into romstage ? this SPD SMB. should be okay to move to romstage. Let me build & test. -- To view, visit https://review.coreboot.org/c/coreboot/+/84405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Gerrit-Change-Number: 84405 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 17:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: vendorcode/amd/fsp/glinda: port usb_phy_config structure
by Marshall Dawson (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk, Maximilian Brune, ritul guru. Marshall Dawson has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84435?usp=email ) Change subject: vendorcode/amd/fsp/glinda: port usb_phy_config structure ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Patchset: PS5: I've reviewed the source content now and it looks good to me. Commit Message: https://review.coreboot.org/c/coreboot/+/84435/comment/bc0c89e8_4257e0a0?us… : PS5, Line 11: Reviewed-by: Anand Vaikar <a.vaikar2021(a)gmail.com> : Reviewed-by: Ritul Guru <ritul.bits(a)gmail.com> : Tested-by: Satya Sreenivas L <Satya.SreenivasL(a)amd.com> : TODO: get you all set up to use util/scripts/cross-repo-cherrypick which will prepend "Original-" to these lines. Would you mind doing that manually here, please, so it keeps the cborg history correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/84435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0603f5da689b6738ea54305a665b150121bc520c Gerrit-Change-Number: 84435 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Oct 2024 16:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/usb/acpi: Add a Power Resource for Intel Bluetooth
by Felix Held (Code Review) 01 Oct '24

01 Oct '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84146?usp=email ) Change subject: drivers/usb/acpi: Add a Power Resource for Intel Bluetooth ...................................................................... drivers/usb/acpi: Add a Power Resource for Intel Bluetooth Add a Power Resource for Intel Bluetooth, that can reset the Bluetooth using the delay configured in the DSM. Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/usb/acpi/usb_acpi.c 1 file changed, 67 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index b01c949..3a9db30 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -129,6 +129,73 @@ }; acpigen_write_dsm_uuid_arr(uuid_callbacks, ARRAY_SIZE(uuid_callbacks)); +/* + * PowerResource (BTRT, 0x05, 0x0000) + * { + * Method (_STA, 0, NotSerialized) + * { + * Return (One) + * } + * Method (_ON, 0, NotSerialized) + * { + * } + * Method (_OFF, 0, NotSerialized) + * { + * } + * Method (_RST, 0, NotSerialized) + * { + * Local0 = Acquire (CNMT, 0x03E8) + * If ((Local0 == Zero)) + * { + * BTRK (Zero) + * Sleep (RDLY) + * BTRK (One) + * Sleep (RDLY) + * } + * Release (CNMT) + * } + * } + */ + acpigen_write_power_res("BTRT", 5, 0, NULL, 0); + { + acpigen_write_method("_STA", 0); + { + acpigen_write_return_integer(1); + } + acpigen_pop_len(); + + acpigen_write_method("_ON", 0); + acpigen_pop_len(); + + acpigen_write_method("_OFF", 0); + acpigen_pop_len(); + + acpigen_write_method("_RST", 0); + { + acpigen_write_store(); + acpigen_write_acquire("CNMT", 0x03e8); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + { + acpigen_emit_namestring("BTRK"); + acpigen_emit_byte(0); + + acpigen_emit_ext_op(SLEEP_OP); + acpigen_emit_namestring("RDLY"); + + acpigen_emit_namestring("BTRK"); + acpigen_emit_byte(1); + + acpigen_emit_ext_op(SLEEP_OP); + acpigen_emit_namestring("RDLY"); + } + acpigen_pop_len(); + acpigen_write_release("CNMT"); + } + acpigen_pop_len(); + } + acpigen_write_power_res_end(); } static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) -- To view, visit https://review.coreboot.org/c/coreboot/+/84146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12 Gerrit-Change-Number: 84146 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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coreboot-gerrit October 2024